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941.
Chuang C.T. Chin K. Stork J.M.C. Patton G.L. Crabbe E.F. Comfort J.H. 《Solid-State Circuits, IEEE Journal of》1992,27(2):225-228
A detailed study on the leverage of high-f T transistors for advanced high-speed bipolar circuit applications is presented. It is shown that for the standard ECL (emitter-coupled logic) circuit, the leverage of high f T is limited by the passive resistors (emitter-follower resistor and collector load resistor) and wire delay, especially in the low-power regime. For the standard NTL (nonthreshold logic) circuit, the leverage is higher due to its front-end configuration and lower power supply value. As the passive resistors are decoupled from the delay path in various advanced circuits utilizing active-pull-down schemes, the leverage of high FT becomes more significant 相似文献
942.
隧道受震破壞調查分析與修復管理案例 总被引:1,自引:0,他引:1
就隧道震後之災損模式進行統計與災損原因研判,並利用數值分析方法研判安全性,就結構加固等改善措施之設計考量作詳細說明;另由於隧道結構物的損壞範圍大,且修復經費受限,必須藉由定期檢测進行長期維護管理,以防範意外發生。於此,利用Vidco-GIS自動化影像地理资訊系統之e化新技術,以動態及靜態影像紀錄隧道災損狀況,同時亦整合建置前期設計、施工圖及定期維護等資料,相關成果以資料庫方式纳入日常維護管理,以有限人力有效率地進行維護管理紀錄並随時掌握現況供作決策之明確參考。 相似文献
943.
Hara H. Sakurai T. Nagamatsu T. Seta K. Momose H. Niitsu Y. Miyakawa H. Matsuda K. Watanabe Y. Sano F. Chiba A. 《Solid-State Circuits, IEEE Journal of》1992,27(11):1579-1584
BiCMOS standard cell macros, including a 0.5-W 3-ns register file, a 0.6-W 5-ns 32-kbyte cache, a 0.2-W 3-ns table look-aside buffer (TLB), and a 0.1-W 3-ns adder, are designed with a 0.5-μm BiCMOS technology. A supply voltage of 3.3 V is used to achieve low power consumption. Several BiCMOS/CMOS circuits, such as a self-aligned threshold inverter (SATI) sense amplifier and an ECL HIT logic are used to realize high-speed operation at the low supply voltage. The performance of the BiCMOS macros is verified using a fabricated test chip 相似文献
944.
Yan R.-H. Lee K.F. Jeon D.Y. Kim Y.O. Park B.G. Pinto M.R. Rafferty C.S. Tennant D.M. Westerwick E.H. Chin G.M. Morris M.D. Early K. Mulgrew P. Mansfield W.M. Watts R.K. Voshchenkov A.M. Bokor J. Swartz R.G. Ourmazd A. 《Electron Device Letters, IEEE》1992,13(5):256-258
The authors report the implementation of deep-submicrometer Si MOSFETs that at room temperature have a unity-current-gain cutoff frequency (f T) of 89 GHz, for a drain-to-source bias of 1.5 V, a gate-to-source bias of 1 V, a gate oxide thickness of 40 Å, and a channel length of 0.15 μm. The fabrication procedure is mostly conventional, except for the e-beam defined gates. The speed performance is achieved through an intrinsic transit time of only 1.8 ps across the active device region 相似文献
945.
946.
Hydrogen Permeability of Borosilicate Glasses 总被引:1,自引:0,他引:1
E. F. Medvedev 《Glass and Ceramics》2002,59(7-8):224-227
Borosilicate glass-forming compositions R2O – B2O3 – SiO2 – RaOb (R — Li, Na, K; Ra — Zn, PbO) are investigated. A correlation-regression analysis of the criteria (the silicate modulus, the oxygen number, the structure cohesion factor, the relative molar volumes of the components) affecting the hydrogen permeability of glasses is carried out. The tendency for permeability variations depending on the component composition and the above specified criteria is identified. 相似文献
947.
N. F. Bondarenko E. Z. Gak M. Z. Gak 《Journal of Engineering Physics and Thermophysics》2002,75(5):1234-1247
This paper gives an overview of the experimental results obtained by the method of MHD modeling in thin electrolyte layers and used to solve problems connected with the appearance of monotonic and vibrational instabilities. Primary consideration is given to the generation and interaction of transient vortex processes. As examples, the results of the investigations of flows in systems of two, three, and four vortices and periodic vortex structures, as well as of flows in the presence of obstacles of different permittivity modeling plants or technogenic screening devices intended to protect objects against pollution are presented. We consider the ways of using the results obtained in studying natural phenomena and in solving engineering-technical problems connected with mass and heat transfer and electrotransmission. 相似文献
948.
Naber J.F. Singh H.P. Tanis W.J. Koshar A.J. Segalla G.L. 《Solid-State Circuits, IEEE Journal of》1992,27(10):1327-1331
An indirect, phase-locked-loop (PLL), GaAs-enhanced frequency synthesizer with 700 ns loop settling time has been developed. The two-chip GaAs insertion reduced the size of an existing synthesizer from 90 in3 to only 30 in3. The 6.0 in×5.5 in.×0.9 in module contains a 400 gate GaAs programmable divider and a sample and hold (S/H) which improved the settling time by 77% and reduced the size by 67% over the current state-of-the-art synthesizer. Furthermore, the divider reduced power dissipation by 9.7 W and the S/H reduced power dissipation by 1.3 W 相似文献
949.
The effect of different amounts (5, 10 and 15%) of compressive deformation of austenite on the isothermal transformation of acicular ferrite in an alloy-steel weld metal has been investigated. It was found that prior deformation of austenite significantly enhanced acicular ferrite transformation. At the same isothermal transformation temperature, as a higher amount of prior deformation was applied, a greater quantity of acicular ferrite could be obtained and the size of acicular ferrite plates became much finer. These results implied that the effective nucleation sites of acicular ferrite increased with increasing amount of prior deformation. The other results also emphasized that the accumulated strain (due to prior deformation of austenite) could trigger acicular ferrite to nucleate on inclusions at high temperatures, where undeformed austenite remained stable. The acicular ferrite start temperature was found to be raised continuously by increasing the amount of prior deformation of austenite. Further evidence suggests that the application of deformation can boost the driving force for acicular ferrite formation. This phenomenon is similar to the case in which martensite forms under the influence of deformation. 相似文献
950.