Influence of multi-finger layout on the subthreshold behavior of nanometer MOS transistors

This work studies the effects of number of gate finger on the DC subthreshold characteristics of multi-finger nanoscale MOS transistors. We found in not optimally-tempered nanoscale (gate length = 90 nm) MOS transistors that the significantly deteriorated subthreshold characteristics can be effectively improved by increasing the number of gate finger. This observation was explained with a modified subthreshold slope model based on voltage-doping transformation theory. Hence, the multi-finger structure does not only enhance the operation frequency, it also improves the subthreshold DC characteristics of the nanoscale MOS transistors.     

Degradation behaviors of GaN light-emitting diodes under high-temperature and high-current stressing

A number of commercially available multiple-quantum well (MQW) InGaN/GaN blue LEDs with wavelengths of about 460 nm and a power of 1 mW were stressed at temperatures ranging from 25 to 120 °C at several accelerated DC currents. Both the forward and reverse current voltage characteristics as well as the electroluminescent spectra of the LEDs were monitored. These effects also resulted in the pronounced degradation of light efficiency and device operation lifetime. We found that the degradation of photonic characteristics, correlated very well with the generation-recombination current which is governed by the defect density. The device degradation is much faster at high temperatures. At nominal operation current and at room temperature, the light intensity degradation reaches a saturation level before the light dyes out. These results shed new lights upon the design and lifetime specifications for the emerging commercial solid-state lighting devices.     

Decision-feedback MAP receiver for time-selective fading CDMAchannels

A decision-feedback maximum a posteriori (MAP) receiver is proposed for code-division multiple-access channels with time-selective fading. The receiver consists of a sequence-matched filter and a MAP demodulator. Output samples (more than one per symbol) from the matched filter are fed into the MAP demodulator. The MAP demodulator exploits the channel memory by delaying the decision and using a sequence of observations. This receiver also rejects multiple-access interference and estimates channel fading coefficients implicitly to give good demodulation decisions. Moreover, computer simulations are performed to evaluate the bit-error rate performance of the receiver under various channel conditions     

摩托罗拉8位HC08微控制器系列

摩托罗拉微控制器(MCU)具有编程语言简单、外围设备齐全、存储器模型用户友好、选择广及供应多、性能价格比高等优点,被设计者评为最容易使用的产品之一。在全球顶级的原始设备制造厂商(OEM)的无数嵌入式系统和用户最终产品中都可找到摩托罗拉的MCU,包括键盘、传呼机、电子游戏机、洗衣机、安全系统及汽车等。     

Ultrahigh‐Working‐Frequency Embedded Supercapacitors with 1T Phase MoSe2 Nanosheets for System‐in‐Package Application

Commercial aluminium electrolyte capacitors (AECs) are too large for integration in future highly integrated electronic systems. Supercapacitors, in comparison, possess a much higher capacitance per unit volume and can be embedded as passive capacitors to address such challenges in electronics scaling. However, the slow frequency response (<10¹ Hz) typical of supercapacitors is a major hurdle to their practical application. Here, it is demonstrated that 1T‐phase MoSe₂ nanosheets obtained by laser‐induced phase transformation can be used as an electrode material in embedded micro‐supercapacitors. The metallic nature of MoSe₂ nanosheet‐based electrodes provides excellent electron‐ and ion‐transport properties, which leads to an unprecedented high‐frequency response (up to 10⁴ Hz) and cycle stability (up to 10⁶ cycles) when integrated in supercapacitors, and their power density can be ten times higher than that of commercial AECs. Furthermore, fabrication processes of the present device are fully compatible with system‐in‐package device manufacturing to meet stringent specifications for the size of embedded components. The present research represents a critical step forward in in‐package and on‐chip applications of electrolytic capacitors.     

Dual-band planar inverted F antenna for GSM/DCS mobile phones

A compact dual-band planar inverted F antenna suitable for the application as a global system for mobile communication/digital communication system (GSM/DCS) dual-band mobile phone internal antenna is proposed and implemented. The proposed antenna has three resonant elements, two meandered metallic strips of slightly different lengths and one nearly-rectangular patch, which are printed on a supporting FR4 substrate and arranged in a compact configuration. These three resonant elements share a common shorting pin, and for the GSM (890-960 MHz) operation, the proposed antenna is operated with the two meandered strips both resonated as a quarter-wavelength structure, leading to a wide bandwidth formed by two resonant modes. For the upper band of the proposed antenna, three resonant modes are generated, two from the second higher-order modes of the two meandered strips and one from the nearly-rectangular patch, leading to a wide bandwidth covering the DCS band (1710-1880 MHz). The antenna design and experimental results are presented.     

A New Method for Blocking Probability Evaluation in OBS/OPS Networks With Deflection Routing

In this paper, we present a new method for the estimation of blocking probabilities in bufferless optical burst or packet switched networks. In such networks, deflection routing is used to reduce blocking probability. However, it requires certain wastage due to trunk reservation that must be used to avoid instability. We provide a wide range of simulation and numerical results to validate our new approximation method and demonstrate various effects on blocking probability and utilization, such as network size, trunk size, the maximal number of allowable deflections, and burst/packet length.     

Self‐Assembled In‐Plane Growth of Mg2SiO4 Nanowires on Si Substrates Catalyzed by Au Nanoparticles

In‐plane growth of Mg₂SiO₄ nanowires on Si substrates is achieved by using a vapor transport method with Au nanoparticles as catalyst. The self‐assembly of the as‐grown nanowires shows dependence on the substrate orientation, i.e., they are along one, two, and three particular directions on Si (110), (100), and (111) substrates, respectively. Detailed electron microscopy studies suggest that the Si substrates participate in the formation of Mg₂SiO₄, and the epitaxial growth of the nanowires is confined along the Si <110> directions. This synthesis route is quite reliable, and the dimensions of the Mg₂SiO₄ nanowires can be well controlled by the experiment parameters. Furthermore, using these nanowires, a lithography‐free method is demonstrated to fabricate nanowalls on Si substrates by controlled chemical etching. The Au nanoparticle catalyzed in‐plane epitaxial growth of the Mg₂SiO₄ nanowires hinges on the intimate interactions between substrates, nanoparticles, and nanowires, and our study may help to advance the developments of novel nanomaterials and functional nanodevices.     

The influence of solder volume and pad area on Sn–3.8Ag–0.7Cu and Ni UBM reaction in reflow soldering and isothermal aging

This paper examines various aspects of SAC (Sn–3.8Ag–0.7Cu wt.%) solder and UBM interactions which may impact interconnection reliability as it scales down. With different solder joint sizes, the dissolution rate of UBM and IMC growth kinetics will be different. Solder bumps on 250, 80 and 40 μm diameter UBM pads were investigated. The effect of solder volume/pad metallization area (V/A) ratio on IMC growth and Ni dissolution was investigated during reflow soldering and solid state isothermal aging. Higher V/A ratio produced thinner and more fragmented IMC morphology in SAC solder/Ni UBM reflow soldering interfacial reaction. Lower V/A ratio produced better defined IMC layer at the Ni UBM interface. When the ratio of V/A is constant, the IMC morphology and growth trend was found to be similar. After 250 h of isothermal aging, the IMC growth rate of the different bump sizes leveled off. No degradation in shear strength was observed in these solder bump after 500 h of isothermal aging.     

Offset compensation in comparators with minimum input-referred supply noise

The resolution of a comparator is determined by the dc input offset and the ac noise. For mixed-mode applications with significant digital switching, input-referred supply noise can be a significant source of error. This paper proposes an offset compensation technique that can simultaneously minimize input-referred supply noise. Demonstrated with digital offset compensation, this scheme reduces input-referred supply noise to a small fraction (13%) of one least significant bit (LSB) digital offset. In addition, the same analysis can be applied to analog offset compensation.