Microscale Patterning of Mesoscopic PZN-PT Single Crystal Films by Crystal ion Slicing and Laser-Induced Etching

Advances in the fabrication of solid-solution single crystal relaxor ferroelectrics have made it possible to produce highly efficient piezoelectric crystals, and have attracted renewed interest in the use of these crystals for a new generation of piezoelectric transducers, actuators and sensors. Of particular interest is their incorporation into micro-electromechanical systems (MEMS). In this paper we report on the laser-induced wet chemical etching of lead zinc niobate-lead titanate (PZN-PT) in hydrochloric acid (HCl). Argon-ion laser radiation at power levels up to 4 W is focused to a spot diameter of about 15μm and results in the chemical etching of grooves at patterning speeds up to 5μm/sec. Crystal ion slicing, an ion-implant-based film separation technique, is used in combination with laser etching to form 5 to 10μm-thick patterned and freestanding films for incorporation into micro-electromechanical devices.     

Valorisation of waste fractions from autohydrolysis of selected lignocellulosic materials

Non‐isothermal processing of lignocellulosic materials in aqueous media (autohydrolysis reaction) under mild conditions leads to solutions containing valuable chemicals (oligosaccharides, sugars and acetic acid) and other, undesired, compounds (belonging to the extractive and acid‐soluble lignin fractions) which have to be removed in further purification treatments. Liquors obtained by non‐isothermal autohydrolysis of Eucalyptus globulus wood and corncobs under a variety of operational conditions were extracted with ethyl acetate in order to remove non‐saccharide components, and the suitability of the fraction dissolved in the organic phase was assayed for possible utilisation as an antioxidant. The yield and antioxidant activity of ethyl acetate extracts (measured by the α,α‐diphenyl‐β‐picrylhydrazyl (DPPH) radical scavenging capacity) showed a strong dependence on the autohydrolysis conditions. The antioxidant activity of extracts obtained under selected operational conditions compared well with synthetic antioxidants. © 2003 Society of Chemical Industry     

Evaluation and optimization of package processing and design through solder joint profile prediction

Solder joints are generated using a variety of methods to provide both mechanical and electrical connection for applications such as flip-chip, wafer level packaging, fine pitch, ball-grid array, and chip scale packages. Solder joint shape prediction has been incorporated as a key tool to aid in process development, wafer level and package level design and development, assembly, and reliability enhancement. This work demonstrates the application of an analytical model and the Surface Evolver software in analyzing a variety of solder processing methods and package types. Bump and joint shape prediction was conducted for the design of wafer level bumping, flip-chip assembly, and wafer level packaging. The results from the prediction methodologies are validated with experimentally measured geometries at each level of design.     

Synthesis of ZSM‐5 Films and Monoliths with Bimodal Micro/Mesoscopic Structures

A route to synthesize ZSM‐5 crystals with a bimodal micro/mesoscopic pore system has been developed in this study; the successful incorporation of the mesopores within the ZSM‐5 structure was performed using tetrapropylammonium hydroxide (TPAOH)‐impregnated mesoporous materials containing carbon nanotubes in the pores, which were encapsulated in the ZSM‐5 crystals during a solid rearrangement process within the framework. Such mesoporous ZSM‐5 zeolites can be readily obtained as powders, thin films, or monoliths.     

An original approximate method for estimating the invariant probability distribution of a large class of multi-dimensional nonlinear stochastic oscillators

This paper proposes an original method for obtaining analytical approximations of the invariant probability density function of multi-dimensional Hamiltonian dissipative dynamic systems under Gaussian white noise excitations, with linear non-conservative parts and nonlinear conservative parts. The method is based on an exact result and a heuristic argument. Its pertinence is attested by numerical tests.     

Derivation of a second-order switching surface in the boundary control of buck converters

A second-order switching surface in the boundary control of buck converters is derived in this letter. The formulated switching surface can make the overall converter exhibit better steady-state and transient behaviors than the one with a first-order switching surface. The switching surface is derived by estimating the state trajectory movement after a switching action, resulting in a high state trajectory velocity along the switching surface. This phenomenon accelerates the trajectory moving toward the target operating point. The proposed control scheme has been successfully applied to a 120-W buck converter. The large-signal performance and a comparison with the first-order switching surface have been studied.     

Influence of device engineering on the analog and RF performances of SOI MOSFETs

This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).     

On the physical and logical topology design of large-scale optical networks

We consider the problem of designing a network of optical cross-connects (OXCs) to provide end-to-end lightpath services to large numbers of label switched routers (LSRs). We present a set of heuristic algorithms to address the combined problem of physical topology design (i.e., determine the number of OXCs required and the fiber links among them) and logical topology design (i.e., determine the routing and wavelength assignment for the lightpaths among the LSRs). Unlike previous studies which were limited to small topologies with a handful of nodes and a few tens of lightpaths, we have applied our algorithms to networks with hundreds or thousands of LSRs and with a number of lightpaths that is an order of magnitude larger than the number of LSRs. In order to characterize the performance of our algorithms, we have developed lower bounds which can be computed efficiently. We present numerical results for up to 1000 LSRs and for a wide range of system parameters such as the number of wavelengths per fiber, the number of transceivers per LSR, and the number of ports per OXC. The results indicate that it is possible to build large-scale optical networks with rich connectivity in a cost-effective manner, using relatively few but properly dimensioned OXCs.     

Static energy reduction techniques for microprocessor caches

Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of static energy consumption due to subthreshold leakage current in cache memory arrays. This paper compares three techniques for reducing static energy consumption in on-chip level-1 and level-2 caches. One technique employs low-leakage transistors in the memory cell. Another technique, power supply switching, can be used to turn off memory cells and discard their contents. A third alternative is dynamic threshold modulation, which places memory cells in a standby state that preserves cell contents. In our experiments, we explore the energy and performance tradeoffs of these techniques. We also investigate the sensitivity of microprocessor performance and energy consumption to additional cache latency caused by leakage-reduction techniques.