Changes in the gaseous H2S barrier properties of damaged silicate coated nylon 6 films

The damage imposed on SiO _x deposited nylon 6 films as a result of abrasion with a cotton cloth and Gelboflex testing was examined by evaluating the rate at which copper plates, which were enveloped by the damaged films, were corroded by H₂S. Abrasion with a cotton cloth caused some micro-cracking of the SiO _x layer and the permeation rate of H₂S approached that of the uncoated nylon 6 film. Damage to the SiO _x layer by twisting and crushing progressed gradually with the number of Gelboflex test cycles and correspondingly the corrosion rate of the copper plates increased. Comparison of the corrosion rates of the copper plates kept in the pouches made of various commercial films with those obtained for the damaged SiO _x deposited nylon 6 films showed a clear relationship between the H₂ permeation rate of the films and the corrosion rate of the copper plates by H₂S.     

A 1-V 10.7-MHz switched-opamp bandpass /spl Sigma//spl Delta/ modulator using double-sampling finite-gain-compensation technique

A 1 V switched-capacitor (SC) bandpass sigma-delta (/spl Sigma//spl Delta/) modulator is realized using a high-speed switched-opamp (SO) technique with a sampling frequency of up to 50 MHz, which is improved ten times more than prior 1 V SO designs and comparable to the performance of the state-of-the-art SC circuits that operate at much higher supply voltages. On the system level, a fast-settling double-sampling SC biquadratic filter architecture is proposed to achieve high-speed operation. A low-voltage double-sampling finite-gain-compensation technique is employed to realize a high-resolution /spl Sigma//spl Delta/ modulator using only low-DC-gain opamps to maximize the speed and to reduce power dissipation. On the circuit level, a fast-switching methodology is proposed for the design of the switchable opamps to achieve a switching frequency up to 50 MHz. Implemented in a 0.35-/spl mu/m CMOS process (V/sub TP/=0.82 V and V/sub TN/=0.65 V) and at 1 V supply, the modulator achieves a measured peak signal-to-noise-and-distortion ratio (SNDR) of 42.3 dB at 10.7 MHz with a signal bandwidth of 200 kHz, while dissipating 12 mW and occupying a chip area of 1.3 mm/sup 2/.     

Crosstalk between microstrip transmission lines

Methods for prediction of crosstalk between microstrip transmission lines are reviewed and simplified for the weak-coupling case. Classical coupled transmission line theory is used for uniform lines, and potential and induced EMF methods are used for crosstalk between nonuniform lines. It is shown that the potential method is equivalent to classical coupled transmission line theory for the case of uniform lines. An experiment was performed for uniform coupled microstrip lines for frequencies from 50 MHz to 5 GHz, and good agreement between theory and measurement was obtained for both near- and far-end crosstalk     

High-frequency analysis of the Ellipticus antenna

Efficient numerical solution techniques have been developed and used to examine the electromagnetic fields that can be developed in the working volume of the CW Ellipticus antenna operated at frequencies from 100 kHz to 1 GHz. An exponentially tapered transition section is designed to obtain the desired illumination pattern in the working volume. The input transition section is needed for impedance matching and to drive efficiently the Ellipticus antenna. A parametric study is performed to ascertain the performance of the Ellipticus antenna for frequencies up to 1 GHz     

Novel level-identifying circuit for flash multilevel memories

This paper presents a high-speed, small-area circuit specifically designed to identify the levels in the read out operation of a flash multilevel memory. The circuit is based on the analog computation of the Euclidean distance between the current read out from a memory cell and the reference currents that represent the different logic levels. An experimental version of the circuit has been integrated in a standard double-metal 0.7-μm CMOS process with a die area of only 140×100 μm². Operating under a 5-V power supply, this circuit identifies the read-out current of a memory cell, and associates it with the appropriate logic level in 9 ns     

High-performance automatic target recognition through data-specificVLSI

Under the Mojave configurable computing project, we have developed a system for achieving high performance on an automatic target recognition (ATR) application through the use of configurable computing technology. The ATR system studied here involves real-time image acquisition from a synthetic aperture radar (SAR). SAR images exhibit statistical properties which can be used to improve system performance. In this paper, the Mojave configurable computing system uses field programmable gate arrays (FPGA's) to implement highly specialized circuits while retaining the flexibility of programmable components. A controller sequences through a set of specialized circuits in response to real-time events. Computer-aided design (CAD) tools have been developed to support the automatic generation of these specialized circuits. The resulting configurable computing system achieves a significant performance advantage over the existing solution, which is based on application specific integrated circuit (ASIC) technology