A methodology for product mix planning in semiconductor foundrymanufacturing

Since a semiconductor foundry plant manufactures a wide range of memory and logic products using the make-to-order business model, the product mix is an important production decision. This paper first describes the characteristics of the product mix planning problem in foundry manufacturing that are attributable to the long flow time and queuing network behaviors. The issues of time bucket selection, mix optimization and bottleneck-based planning are next addressed. A decision software system based on integer linear programming techniques and a heuristic procedure has been implemented for mix planning. Data provided by a wafer plant has been used to study problems related to product mix planning. It was determined that the suitable time bucket of planning is either one week or one month and the lead-time offset factor should be included in the logic of workload calculation. This paper also presents various facets of product mix decisions and how they should be integrated with operations management     

IMPACCT: Methodology and Tools for Power-Aware Embedded Systems

Power-aware systems are those that must exploit a widerange of power/performance trade-offs in order to adapt to the power availabilityand application requirements. They require the integration of many novel powermanagement techniques, ranging from voltage scaling to subsystem shutdown.However, those techniques do not always compose synergistically with eachother; in fact, they can combine subtractively and often yield counterintuitive,and sometimes incorrect, results in the context of a complete system. Thiscan become a serious problem as more of these power aware systems are beingdeployed in mission critical applications.To address the problem of technique integration for power-aware embedded systems, we propose a new design tool framework called IMPACCT and the associated design methodology. The system modeling methodology includes application model for capturing timing/powerconstraints and mode dependencies at the system level. The tool performs power-awarescheduling and mode selection to ensure that all timing/power constraintsare satisfied and that all overhead is taken into account. IMPACCT then synthesizesthe implementation targeting a symmetric multiprocessor platform. Experimentalresults show that the increased dynamic range of power/performance settingsenabled a Mars rover to achieve significant acceleration while using lessenergy. More importantly, our tool correctly combines the state-of-the-arttechniques at the system level, thereby saving even experienced designersfrom many pitfalls of system-level power management.     

Benzodithiophene Hole‐Transporting Materials for Efficient Tin‐Based Perovskite Solar Cells

Developing efficient interfacial hole transporting materials (HTMs) is crucial for achieving high‐performance Pb‐free Sn‐based halide perovskite solar cells (PSCs). Here, a new series of benzodithiophene (BDT)‐based organic small molecules containing tetra‐ and di‐triphenyl amine donors prepared via a straightforward and scalable synthetic route is reported. The thermal, optical, and electrochemical properties of two BDT‐based molecules are shown to be structurally and energetically suitable to serve as HTMs for Sn‐based PSCs. It is reported here that ethylenediammonium/formamidinium tin iodide solar cells using BDT‐based HTMs deliver a champion power conversion efficiency up to 7.59%, outperforming analogous reference solar cells using traditional and expensive HTMs. Thus, these BDT‐based molecules are promising candidates as HTMs for the fabrication of high‐performance Sn‐based PSCs.     

Fabrication process simulation and reliability improvement of high-brightness LEDs

To enhance the light extraction efficiency and thermal performance of AlGaInP light-emitting diodes (LEDs), the wafer bonding technique which can replace the GaAs substrate with other high thermal conductivity substrates was applied. However, this technique may make the film crack during either the removal etching process of the GaAs substrate or the annealing process after the GaAs removal. Therefore, this crack problem is an important issue in the reliability/yield of high-brightness LEDs. In this research, a detailed finite element model of the high-brightness AlGaInP LED, which is replaced by the GaAs substrate with high thermal conductivity substrate through the Au–In metal bonding technique, was developed and fabricated. In addition, the mechanical behavior of wafer-level metal bonding was also simulated by finite element analysis (FEA) and validated by experimental measurements. Hence, the above validated simulation technique combined with process modeling is used to understand the stress variation of the multilayer structure of AlGaInP LED during the fabrication process and to find the principal cause of the film crack.     

Novel Optical Phase Demodulator Based on a Sampling Phase-Locked Loop

A novel phase-locked coherent demodulator, based on a sampling phase-locked loop, is presented and investigated theoretically. The demodulator is capable of operating at high frequencies, by using optical sampling to downconvert the high-frequency input radio-frequency signal to the frequency range of the baseband loop. We develop a detailed theoretical model of the (sampling) phase-locked coherent demodulator and perform detailed numerical simulations. The simulation results show that the operation of the sampling demodulator resembles the operation of the baseband demodulator for very short optical pulses (<2 ps). Furthermore, we investigate how the signal-to-noise ratio of the demodulator is affected by timing and amplitude jitter of the pulsed optical source     

Dithering and its effects on sigma-delta and multistage sigma-delta modulation

The spectrum of the quantization error in a dithered sigma-delta modulator is derived under the constraint that the dithering signal does not cause overload. The results apply to DC, sinusoidal, and more general quasi-stationary signals. It is shown in the case of a simple sigma-delta modulation that no-overload dithering can smooth the error spectrum and can make the quantization error asymptotically uncorrelated with the input. It does not, however, make the quantization error white. In the case of multistage sigma-delta modulation with the appropriate dithering, the quantization error becomes white, even for a system with only two stages. The signal-to-quantization-noise ratio (SQNR) is derived for sigma-delta and multistage sigma-delta oversampled analog-to-digital conversion with additive dithering. Simulation results, are presented to support the theoretical analysis.<>     

Optimization of the host/vector system and culture conditions for production of penicillin acylase in Escherichia coli

Culture performance for the production of penicillin acylase (PAC) in a bioreactor was investigated using HB101 or ATCC11105 as the host and pCLL2902, pCLL3201 or pTrcKnPAC2902 as the expression plasmid. We observed that the production of PAC by HB101 harboring pCLL3201 was, similar to ATCC11105, induced by phenyl acetic acid (PAA) and catabolicaily repressed by glucose, whereas the production of PAC by HB101 harboring pCLL2902 did not require PAA for induction and was not repressed by glucose. PAC activity of HB101 harboring pCLL2902 was significantly higher than that of HB101 harboring pCLL3201. There was no significant effect of host or carbon source on the production of PAC using pCLL2902. The production of PAC by HB101 harboring pTrcKnPAC2902, in which the pac gene expression was controlled by the trc promoter system, was about the same as that by HB101 harboring pCLL2902, when the culture was appropriately induced with isopropyl beta-d-thiogalactopyranoside (IPTG). Therefore, the use of both pCLL2902 and pTrcKnPAC2902 could be expected to be feasible for industrial applications. However, optimization of IPTG induction for HB101 harboring pTrcKnPAC2902 might be required, since formation of inclusion bodies tends to limit the production of PAC in some cases.     

An eccentrically coated asymmetric antenna applicator forintracavitary hyperthermia treatment of cancer

In this paper a model based on transmission line theory is used to predict the behavior of an eccentrically coated asymmetric antenna applicator for use in intracavitary hyperthermia. Theoretical results for the heating rate (HR) of the applicators are compared to experimental results. The experimental results were obtained at City of Hope National Medical Center using four different 915-MHz applicators, each with a different antenna size and eccentricity of the coating. A parameter delta is defined where delta < 1.0 is a thin wire approximation; delta is primarily a function of the eccentricity of the coating, the antenna diameter, and the coating diameter. It is found that when delta approximately less than 0.5, the theoretical model works well. In particular, it predicts the directivity due to the eccentricity of the coating. However, as this eccentricity is increased or as the antenna diameter is increased (delta approximately greater than 0.6), the model no longer accurately predicts directivity. Thus, the model that can be used to predict the HR profiles for an eccentrically coated asymmetric antenna only when delta approximately less than 0.5.     

A WH/GSMT-based full-wave analysis for planar transmission linesembedded in multilayered dielectric substrates

A new full-wave analysis method, referred to as the WH/GSMT, is developed to solve multilayered planar transmission line problems. First, the scattering of an obliquely incident parallel plate mode (PPM) by a PEC half plane embedded in a multilayered isotropic dielectric substrate within a PEC parallel plate region is analyzed via the Wiener-Hopf (WH) technique. The solution is then incorporated into the generalized scattering matrix technique (GSMT) to find the (complex) propagation constant and characteristic impedance of the planar transmission lines. The lateral power leakage is taken into account rigorously in the WH/GSMT. Numerical results including the microstrip line, conductor-backed slotline, coupled microstrip lines, and antipodal finlines are presented along with a discussion of the advantages/disadvantages of this method     

On general zero-skew clock net construction

We propose a simulated annealing based zero-skew clock net construction algorithm that works in any routing spaces, from Manhattan to Euclidean, with the added flexibility of optimizing either the wire length or the propagation delay. We first devise an O(log n) tree grafting perturbation function to construct a zero-skew clock tree under the Elmore delay model. This tree grafting scheme is able to explore the entire solution space asymptotically. A Gauss-Seidel iteration procedure is then applied to optimize the Steiner point positions. Experimental results have shown that our algorithm can achieve substantial delay reduction and encouraging wire length minimization compared to previous works