一种基于优先级的TDMA时隙接入算法

文章为TDMA时隙动态调整提供一种基于优先级的随机统一多址接入算法,通过用户的平台类型、用户的活动因子和新入网以及已经在网的用户,考虑用户的优先级和平台类型的优先级实现时隙的动态调整和时隙复用,解决了TDMA网络的不同类型用户信息传输时隙分配问题。     

Pseudo-Noise Code Shifting Signal for AI Arranged UAV Networking

Mobile Networks and Applications - Communication problems standout as the key issue needing to be addressed in Unmanned Aerial Vehicle (UAV) applications. Nowadays, the application of Artificial...     

Structure optimization of polymeric Mach-Zehnder rib waveguide

The polymeric material is very promising for fabricating the integrated optical waveguide devices. The polymeric op- tical waveguide has become the hotspot because the poly- meric material can offer a series of merits, such as easy integration, rapid resp…     

几种国产天然气传感器的性能对比及评价

通过对几种国产半导体天然气传感器与世界名牌FIGARO公司产TGS813的对比评价看出，尽管外观和响应特性上有很多相似之处，但在初期特性、温湿度特性、长期稳定性上还存在很大差距。从内部结构解析的观察结果可以看出，在一些生产工序中存在着很大的潜在隐患，但是这些差距对一般用户来说很难了解。本文对其判断方法进行了详细叙述。     

Cloud service provisioning in two types of DCN with awareness of delay and link failure probability

Cloud service based on data center network (DCN) has become an attractive choice for various applications. Traditionally, multiple DCs are distributed at different nodes across a given optical network, and users access DCs through predefined routes (this architecture is named as Multiple Independent DCN, MI-DCN). However, as there exist transmission delay and failure probability on each link, such a network may not be a good choice for the service providers from the perspective of service reliability and cost. Therefore, we propose the idea of regrouping all the racks and distributing each rack group on a special node, where there exists a gateway (this architecture is named as Integrated Distributed DCN, ID-DCN). As each group can provide service independently, by properly grouping and routing, the whole network can work more efficiently with lower cost and higher reliability. In this paper, we study the service provision in the above two types of DCN. With the given failure probability and transmission delay on each link, we aim to minimize the total service cost and design the access routes for the demands originated from each node. To integrate the system cost, we introduce two cost scaling factors for delay and failure probability, which can be flexibly adjusted to control their relative importance (i.e., the weights). Based on mathematical approximation, a novel method is proposed to compute the failure probabilities of individual service paths. This translates our objective function into a linear expression. Then, we formulate two integer linear programs (ILP) to compare the solutions of the two scenarios. Via extensive numerical experiments, the performance of the two schemes is properly verified.     

Cooperative detection and protection for Interest flooding attacks in named data networking

Named data networking (NDN) is a new emerging architecture for future network, which may be a substitute of the current TCP/IP‐based network, for the content‐oriented data request mode becoming the future trend of development. The security of NDN has attracted much attention, as an implementation of next‐generation Internet architecture. Although NDN is immune to most current attack, it cannot resist the distributed denial of service like attack – Interest flooding attack (IFA) – effectively. IFA takes advantages of the forwarding mechanism of NDN, flooding a large number of malicious Interest packets at quite a high rate, and exploits the network resources, which may cause the paralysis of the network. Taking into account the severity of the destruction, we propose an algorithm to counter such new type of attack. We analyze three properties of IFA, and use them to judge and filter Interest packets. Vector space model and Markov model are used in our method to realize a cooperative detection. Meanwhile, we present the retransmission forwarding mechanism to ensure legitimate user request. The ndnSIM module of ns3 is used for the corresponding simulation, and results of the simulation will be given to show the effectiveness of our algorithm. Copyright © 2014 John Wiley & Sons, Ltd.     

Energy efficiency optimization for HCNs based on small base station transmission power allocation

In the research of green communication, considering the base station (BS) power allocation from the perspective of energy efficiency (EE) is meaningful for heterogeneous cellular networks (HCNs) optimization. The EE of two-tier HCNs was analyzed and a new method for the network EE optimization was proposed by adjusting the small BS transmitting power. First, the HCNs ware modeled by homogeneous Poisson point processes (PPPs), and the coverage probability of BSs in each tier was derived. Second, according to the definition of EE, and the closed-form of EE was given by deriving the total power consumption and total throughput of HCNs respectively. At last, the analytical performance of the EE of HCNs on the small BS transmission power was analyzed, and a small BS power optimization algorithm was proposed to maximize the EE. Simulation results show that, the transmission power of small BS has a significant impact on the EE of HCNs. Furthermore, by optimizing the transmission power of small BS, the EE of HCNs can be improved effectively.     

武器装备故障诊断专家系统平台的初步设计

介绍了专家系统平台的概念及在军事领域中应用的意义.详细描述了建立专家系统平台的知识表示和推理方式等关键内容.提出了一种多知识表示、多推理方式的故障诊断专家系统平台.     

防空多管火箭武器跟踪发射模型研究

立足于火箭武器发展的需求,研究了防空多管火箭炮的跟踪运动对火箭弹离轨参数的影响,给出了跟踪发射时火箭弹运动参数的计算方法,确定了火箭弹脱离定向器瞬时的运动参数,获得了空间弹道计算的初始条件,同时研究了两种特殊跟踪运动下火箭弹的离轨参数,为火箭弹飞行性能优化和发射装置的设计提供了参考。     

Single-Chip Eye Tracker Using Smart CMOS Image Sensor Pixels

The eye tracker is a system that detects the point where the user gazes on. The conventional eye tracker using a Charge-Coupled Device (CCD) camera needs many peripherals and software computation causing high cost, computation time and power consumption. This paper proposes a single-chip eye tracker using smart CMOS Image Sensor (CIS) pixels. The proposed eye tracker does not require additional peripherals and operates at higher speed than the conventional approach. The prototype chip was designed and fabricated for a 32 × 32 smart CIS pixels array with a 0.35-μ m CMOS process. The test results show ± 1 pixel error at the rate of 125 frame-per-second. The power consumption is 260 mW with 3.3 V supply voltage and the silicon area is 3.8 mm²