Hough transform using Cordic method

The purpose of the letter is to demonstrate the usefulness of the Cordic algorithm for implementation of image processing algorithms in dedicated hardware to achieve near real-time processing speed. The Cordic algorithm will be discussed, and also its application for line and circle detection as well as for arbitrary shapes using Hough transforms.<>     

Realization of transmission-gate conditional-sum (TGCS) adders withlow latency time

Transmission conditional-sum (TGCS) adders realized in a standard 2.5-μm CMOS technology are discussed. These adders offer short propagation delay and latency time (12.5 ns for 32-b addition) and consume only moderate chip area (i.e. 80×460 μm² for 1 b in a 32-b adder). They allow static operation and consume only dynamic power (like standard CMOS). The layout exhibits high regularity and can be easily adjusted to various word lengths. Design and layout techniques are described in detail and experimental data are given     

A comparison of semiconductor controlled sources for the design of active rc impedances

A feasibility study of the four types of controlled sources realized in bipolar form is undertaken. The results are used in designing a PCM lowpass filter of which the total amplitude variance due to passive and active non-idealities is minimized. The circuit yield is determined using Monte Carlo simulation. For this particular application, a comparison shows preferable behaviour using transimmitances (e.g. operational transconductance amplifiers) than using gain elements such as the opamp.     

Novel bottom-plate stray-insensitive voltage inverter switch

A novel v.i.s. circuit is proposed which is insensitive to stray capacitances of the bottom plates of m.o.s. capacitors. This circuit configuration allows easy design of higher order filters.     

Time-of-Flight 3-D Imaging Pixel Structures in Standard CMOS Processes

In this investigation we examine different pixel structures and readout principles to be used in imagers fabricated in standard CMOS processes, for example, the 0.5 and 0.35 processes available at the Fraunhofer IMS. The targeted applications are high-speed near-infra-red (NIR) 3-D imaging based on time-of-flight (TOF) measurements. We discuss various issues ranging from charge-coupling possibilities to noise, spectral responsivity and fill-factor, and present an extensive study of pixel configurations based on inverse biased p-n junction and MOS-C based photodetectors. We also discuss the possibilities of using a novel CMOS imaging pixel for TOF imaging applications: the charge-injection photogate (CI-PG) which presents parametric time-compression amplification. Finally, we compare and discuss all the pixel configurations examined.     

A JFET-CMOS radiation-tolerant charge-sensitive preamplifier

A monolithic charge-sensitive preamplifier based on n-channel junction field-effect transistors (JFETs) and p-channel MOS has been realized for applications with microelectrode detectors in elementary particle physics. Radiation resistance tests carried out with the preamplifier exposed to γ-rays emitted by a ⁶⁰Co source have shown no significant increase of the equivalent noise source up to 150-krd absorbed dose     

A programmable CORDIC chip for digital signal processingapplications

A chip implementing the coordinate rotation digital computer (CORDIC) algorithm is described. It contains a 10-MHz 16-b fixed-point CORDIC arithmetic unit, 2-kb RAM, a controller, and input/output (I/O) registers. A modified data-path architecture allows cross-wire free data flow. The chip design involved development of optimized carry-select adders and a modified programmable-logic-array (PLA) cell layout, which allows speed increase in single-layer metal technology. The authors designed, fabricated, and tested a general-purpose fully parallel programmable CORDIC chip in CMOS technology and developed optimal iteration sequences     

Real-time programmable unit-element SC filter for LPC synthesis

The letter presents a novel programmable unit-element SC filter for LPC synthesis. The circuit is based on the theory of wave-flow networks. It has the advantage that for a programmable 10th-order unit-element SC filter only five programmable capacitor arrays are needed. The capacitive loading of every op amp is constant, thus simplifying the op amp design. The circuit is insensitive to stray capacitances which are commonly associated with integrated MOS capacitors and transistors. It also exhibits a low sensitivity to coefficient quantisations; hence, the circuit is well suited for integration in MOS technology.     

Design and applications of tunable analog BiCMOS circuits

Discusses the design, merits, and applications of tunable BiCMOS circuits. Although the BiCMOS technology offers higher design flexibility due to the presence of more types of active devices than the standard CMOS or bipolar technologies, it is also costlier. Hence, its use can be justified only if the salient features of BiCMOS are taken advantage of adequately. The analysis discusses one possible approach that cannot be easily and economically duplicated in other technologies.<>     

A 1 K×1 K high dynamic range CMOS image sensor with on-chipprogrammable region-of-interest readout

An integrated 1024×1024 CMOS image sensor with programmable region-of-interest (ROI) readout and multiexposure technique has been developed and successfully tested. Size and position of the ROI is programmed based on multiples of a minimum readout kernel of 32×32 pixels. Since the dynamic range of the irradiance normally exceeds the electrical dynamic range of the imager that can be covered using a single integration time, a multiexposure technique has been implemented in the imager. Subsequent sensor images are acquired using different integration times and recomputed to form a single composite image. A newly developed algorithm performing the recomputation is presented. The chip has been realized in a 0.5-μm n-well standard CMOS process. The pixel pitch is 10 μm² and the total chip area is 164 mm ²