High performance analog VLSI computational circuits

Simple linear voltage/current-controlled voltage-to-current (V-T) converters, which are to first-order insensitive to the threshold voltage variation, are introduced. The circuits can be used as basic building blocks to construct simple analog computational circuits, which can perform functions such as square rooting, squaring, multiplication, sum of squares, difference of squares, etc. Some of the key features are: good linearity, floating inputs [high common-mode rejection ratio (CMRR)], simplicity, and good transconductance tuning range. The circuits can be realized with CMOS devices in saturation, however, BiCMOS devices extend their speed and input voltage range. Realistic simulations and experimental results clearly demonstrate the claims     

Hop-timing estimation for FH signals using a coarsely channelizedreceiver

This paper addresses new hop-timing (epoch) estimation schemes which employ a coarsely channelized preprocessor in order to suppress the frequency and phase dependence in random frequency-hopping (FH) signals. Coarse channelization implies a bank of filters, covering the total spread bandwidth of the FH signal, whose number is much smaller than the size of the candidate hop frequency set. Linear and nonlinear combinations of preprocessor outputs are explored and compared. It is found that post-processing, rather than the size of the filter bank alone, is the determining factor on estimation performance. Performance evaluation is presented via both extensive computer simulations and analytical lower bounds. Comparisons with existing optimal and suboptimal systems are also provided     

Design of Si/SiGe heterojunction complementarymetal-oxide-semiconductor transistors

An optimized Si/SiGe heterostructure for complementary metal-oxide semiconductor (CMOS) transistor operation is presented. Unlike previous proposals, the design is planar and avoids inversion of the Si layer at the oxide interface. The design consists of a relaxed Si_0.7Ge _0.3 buffer, a strained Si quantum well (the electron channel), and a strained S_1-xGe_x (0.7>x>0.5) quantum well (the hole channel). The channel charge distribution is predicted using a 1-D analytical model and quantum mechanical solutions. Transport is modeled using 2-D drift-diffusion and hydrodynamic numerical simulations. An almost symmetric performance of p- and n-transistors with good short-channel behavior is predicted. Simulated ring oscillators show a 4- to 6-fold reduction in power-delay product compared to bulk Si CMOS at the 0.2-μm channel length generation     

Quantum phenomena in field-effect-controlled semiconductornanostructures

Quantum effects resulting from sub-100 nm features in planar, field-effect-controlled semiconductor structures or devices are discussed, and experimental results are compared with calculations. These devices are based on the GaAs-AlGaAs modulation-doped field-effect transistor (MODFET) and include grating-gate lateral surface superlattices. (LSSLs), grid-gate LSSLs, planar-resonant-tunneling field-effect transistors (PRESTFETs), multiple parallel quantum wires (MPQWs), and arrays of quantum dots (QDs). In contrast to conventional, epitaxially grown vertical quantum structures, planar structures offer the opportunity for electron confinement in three, two, and one dimensions and the flexibility of electrical tuning of quantum effects     

Physical and geochemical properties of crude oils in relation to their source rocks,Alif field,Marib Sub-basin,Yemen

Physical and geochemical properties were performed on three crude oils from Alif-01 well in the Marib sub-basin. The analyzed samples comprise medium specific gravity (37^° API), reflecting mature source rocks. The thermal maturity of the analyzed oils is also indicated from the high content of aliphatic hydrocarbons (HC). The compositions of HC further suggest that analyzed oils belong to paraffinic oils. The n-alkane and isoprenoid distributions reveal that the analyzed oils are derived from marine source rock, containing mixed organic matter, with some terrestrial input and deposited under relatively reducing conditions. The features of the analyzed oils are consistent with the Madbi source rock characteristics in the basin.     

Optical Nanoscale Pool‐on‐Surface Design for Control Sensing Recognition of Multiple Cations

General design of optical chemical nanosensors is needed to develop efficient sensing systems with high flexibility, and low capital cost for control recognition of toxic analytes. Here, we designed optical chemical nanosensors for simple, high‐speed detection of multiple toxic metal ions. The systematic design of the nanosensors was based on densely patterned chromophores with intrinsic mobility, namely, “building‐blocks” onto three‐dimensional (3D) nanoscale structures. The ability to precisely modify the nanoscale pore surfaces by using a broad range of chromophores that have different molecular sizes and characteristics enables detection of multiple toxic ions. A key feature of this building‐blocks design strategy is that the surface functionality and good adsorption characteristics of the fabricated nanosensor arrays enabled the development of “pool‐on‐surface” sensing systems in which high flux of the metal analytes across the probe molecules was achieved without significant kinetic hindrance. Such a sensing design enabled sensitive recognition of metal ions up to sub‐picomolar detection limits (～10^?11 mol dm^?3), for first time, with rapid response time within few seconds. Moreover, because these sensing pools exhibited long‐term stability, reversibility and selectivity in detecting most pollutant cations, for example, Cr(VI), Pb(II), Co(II), and Pd(II) ions, they are practical and inexpensive. The key result in our study is that the pool‐on‐surface design for optical nanosensors exhibited significant ion‐selective ability of these target ions from environmental samples and waste disposals.     

A Differential CMOS Current-Mode Variable Gain Amplifier with Digital dB-Linear Gain Control

A novel CMOS variable gain amplifier operating on current signals with a dB-linear gain control is presented. The gain control is achieved by multiplying a digitally synthesized exponentially varying control current signal by a differential input signal in the current domain. A current amplifier at the output sets the gain to the desired level. Current-mode operation allows for a reduced supply voltage by minimizing the voltage swing at the low impedance nodes of the circuit. Multiple circuit realizations for various blocks are presented allowing for designs meeting different constraints. Experimental realization of the variable gain amplifier shows the validity of the presented approach.     

Multiple Threshold Voltage Design Scheme for CMOS Tapered Buffers

This brief proposes lower power lower delay design for CMOS tapered buffers. A slight increase in the threshold voltage is shown to have an exponential effect in reducing the total power dissipation. The corresponding increase in the propagation delay is compensated for by increasing the number of buffer stages such that there is still an overall significant reduction in the total power dissipation. As compared to the constant threshold voltage design based on a cost function of PT², the proposed scheme can lead to either a power dissipation reduction of about 70% while maintaining the same delay, or up to 30% in power dissipation with 10% propagation delay reduction, respectively, in 65-nm technology with V_DD = 1 V, minimum size gate capacitance, C_g = 1.5 fF, and minimum size output capacitance, C_o = 1 fF. Closed-form expressions that give the optimum threshold voltage and number of stages are presented.     

Design of CMOS VHF/RF Biquadratic Filters

In this paper, a class of CMOS biquadratic filter suitable to work at VHF/RF frequency range is presented. The proposed circuit has a simple structure which is analyzed and designed according to a universal G _m-C biquad filter. Simulation and experimental results show that these filters can work in GHz range and have wide tuning range.     

A 10-GHz CMOS quadrature LC-VCO for multirate optical applications

A 10-GHz quadrature LC-VCO (QVCO) fabricated in a 0.13-/spl mu/m CMOS process for 10-Gb/s multirate optical applications is described. Bimodal oscillation behavior (or phase ambiguity) inherent to quadrature LC-VCOs is analyzed theoretically and a cascode-based coupling method is proposed which effectively eliminates bimodal oscillation. Digitally controlled capacitor arrays are used in this design to extend the tuning range of the QVCO to cover multirate operations. The QVCO achieves a jitter generation of only 32 mUI/sub pp/ at 10 GHz and a phase noise of -95 dBc/Hz at 1-MHz frequency offset with only 8 mA of current consumption in the QVCO core.