基于移动Agent技术的QoS保障机制

介绍了移动Agent的基本特性。移动Agent可在异构的网络各个节点间自由地移动,它能感知网络的状态,监控系统并与其他Agent进行交互。IETF的IS模型采用了RSVP(ResourcereSerVationProtocol)协议对系统资源进行预留,从而达到一定程度上保障所需QoS的目的。QoS保障机制将移动agent技术与RSVP协议结合起来,通过资源预留和agent动态移动的实现可以达到更好地改善QoS的目的。     

Suppression of boron penetration in p+ polysilicon gateP-MOSFETs using low-temperature gate-oxide N2O anneal

It has been reported that high-temperature (~1100°C) N₂ O-annealed oxide can block boron penetration from poly-Si gates to the silicon substrate. However, this high-temperature step may be inappropriate for the low thermal budgets required of deep-submicron ULSI MOSFETs. Low-temperature (900~950°C) N₂O-annealed gate oxide is also a good barrier to boron penetration. For the first time, the change in channel doping profile due to compensation of arsenic and boron ionized impurities was resolved using MOS C-V measurement techniques. It was found that the higher the nitrogen concentration incorporated at Si/SiO₂ interface, the more effective is the suppression of boron penetration. The experimental results also suggest that, for 60~110 Å gate oxides, a certain amount of nitrogen (~2.2%) incorporated near the Si/SiO₂ interface is essential to effectively prevent boron diffusing into the underlying silicon substrate     

The hydration phase and pore structure formation in the blends of sulfoaluminate-belite cement with Portland cement

Sulfoaluminate-belite (SAB) cements are an attractive class of low-energy cements from the viewpoint of saving energy and releasing less CO₂ into the atmosphere during their production. Their hydraulic activity, however, does not match that of the ordinary Portland cement (PC) and needs improvement before they can be used on their own. However, SAB cements when blended with PC have the potential to be used effectively in traditional applications as shown by this study. Mortars made with blends of SAB cements and PC, and a cement-to-sand ratio of 1:3 by weight and a water-to-cement ratio of 0.5, indicate a superior protection against corrosion of steel to those made with blends of PC and blast-furnace slag (BFSPC). The prepared mortars were stored at 20 °C for 90 days under either a 60% relative humidity (RH)-dry air, or 100% RH-wet air conditions. With further improvement in the SAB cement quality through better understanding of their characteristics, a genuine competition between SAB/PC and BFSPC can be expected in practice.     

Testability-analysis driven test-generation of analogue cores

A new definition of the testability transfer factor for circuit components that provides better sensitivity with respect to parametric deviations is presented. New equations for the testability measures in a mixed-signal core are given. Testability analysis is used for test-pattern generation and for consideration of inserting wrapper cells. The simulation results show the effectiveness of the approach.     

Kinetic Monte-Carlo simulation of network formation

Summary the simulation described in Part I was applied to random step polyaddition of a trifunctional monomer and the results were compared with exact solution for an infinite system. The gel point conversions, the weight-average degree of polymerization before (P _w) and beyond (P _w,sol) the gel point, the sol fraction and the cycle rank were used for comparison. The best way for detection of the gel point conversion is the extrapolation of the gel fraction, w _g, to w _g=0. The largest fluctuations are exhibited by P _w and P _w,sol. To get results closer to the exact ones, one can repeat several experiments with smaller number of units or increase the number of units, the former way being somewhat more economical. Typical orders of magnitude used were 10⁷ monomeric units.     

Short-circuit power driven gate sizing technique for reducing powerdissipation

One major challenge in low-power technology is how to reduce overall power dissipation of a given subsystem without impacting its performance. In this paper we present a technique that can be applied to the nonspeed-critical nets in a circuit in order to reduce overall power dissipation. This technique involves a study of short-circuit power dissipation as a function of input signal slews and output load conditions, to aid in making a judicious choice of drive strengths for various gates in a circuit. The resulting low-power solution does not degrade the original performance and yields a circuit which occupies less silicon area. The technique described here can be incorporated into any power optimization or synthesis tool. Lastly, we present the savings in power and area for a 32-b carry lookahead adder which was designed using the technique described here