Developing a conductive oxygen barrier for ferroelectric integration

For high-density FeRAM memories, the 1T–1C architecture has been proposed. In this scheme, the ferrocapacitor (FeCAP), a metal\ferroelectric film\metal-like sandwich, is placed directly on top of polysilicon or tungsten plugs contacted to the underlying CMOS technology. Our ferroelectric material of choice, SrBi₂Ta₂O₉ (SBT), requires crystallization anneals ranging from 650 to 800 °C in full oxygen. The bottom electrode (BE) needs to be conductive, as well as an oxygen barrier to protect the underlying plug from oxidation. We have developed a BE stack combination consisting of Pt/IrO₂/Ir/Ti(Al)N. Each layer plays a critical role in the performance of the barrier. Issues such as thermal expansion, stress relaxation, grain growth, and oxidation can be critical in order to have a working bottom electrode. For capacitor formation, the complete stack is etched and covered by SBT. Since all layers are in contact with SBT, it is important to understand how the ferroelectric interacts with both the individual layers and the combined structure. In this paper, we will present our understanding of the chemical reactivity between SBT and the BE stack, which has been successfully engineered to prevent oxidation of the underlying plug.     

Voltage pulses change neural interface properties and improve unit recordings with chronically implanted microelectrodes

Current neuroprosthetic systems based on electrophysiological recording have an extended, yet finite working lifetime. Some posited lifetime-extension solutions involve improving device biocompatibility or suppressing host immune responses. Our objective was to test an alternative solution comprised of applying a voltage pulse to a microelectrode site, herein termed "rejuvenation." Previously, investigators have reported preliminary electrophysiological results by utilizing a similar voltage pulse. In this study we sought to further explore this phenomenon via two methods: 1) electrophysiology; 2) an equivalent circuit model applied to impedance spectroscopy data. The experiments were conducted via chronically implanted silicon-substrate iridium microelectrode arrays in the rat cortex. Rejuvenation voltages resulted in increased unit recording signal-to-noise ratios (10%/spl plusmn/2%), with a maximal increase of 195% from 3.74 to 11.02. Rejuvenation also reduced the electrode site impedances at 1 kHz (67%/spl plusmn/2%). Neither the impedance nor recording properties of the electrodes changed on neighboring microelectrode sites that were not rejuvenated. In the equivalent circuit model, we found a transient increase in conductivity, the majority of which corresponded to a decrease in the tissue resistance component (44%/spl plusmn/7%). These findings suggest that rejuvenation may be an intervention strategy to prolong the functional lifetime of chronically implanted microelectrodes.     

Lead-free solder flip chip-on-laminate assembly and reliability

This paper examines the assembly process for flip chip die with SnAgCu solder bumps and the results of liquid-to-liquid thermal shock testing. The SnAgCu alloy required a thicker dip layer of flux to achieve good wetting compared to the SnPb eutectic alloy. A liquid spray flux yielded more consistent solder wetting with the SnAgCu alloy. With both fluxes, a nitrogen reflow atmosphere was necessary with the SnAgCu alloy. A peak reflow temperature of 246°C was used for the assembly of the SnAgCu thermal shock test vehicles. A lower peak temperature of 235°C did not yield sufficient solder wetting. Liquid-to-liquid thermal shock testing was performed from -40°C to +125°C. The SnPb alloy performed slightly better than the SnAgCu and the dip flux was better that the spray flux. The degree of delamination with the SnAgCu alloy was significantly higher than with the SnPb alloy. Cracks in the underfill between adjacent solder balls were observed. The SnPb alloy extruded into these cracks more readily than the SnAgCu and created electrical shorts     

Investigation of the Role of Void Formation at the Cu-to-Intermetallic Interface on Aged Drop Test Performance

Chip-scale packages (CSPs) are widely used in portable electronic products. Mechanical drop testing is a critical reliability requirement for these products. With the switch to lead-free solder, new reliability data must be generated. Most drop test reliability data reported for CSPs are for the as-built condition. However, the mechanical shock reliability over the life of the product is equally important. This paper provides a systematic study of surface finish (immersion Sn and immersion Ag) and reflow profile (cool down rate) on the drop test reliability of CSP assemblies. A limited experiment was also performed with organic solderability preservative (OSP)-coated boards. The Sn finish provides an initial Cu-Sn intermetallic layer, while the Ag finish and OSP coating allows the formation of the initial Cu-Sn intermetallic during the reflow cycle. Drop test results for assemblies as-built and as a function of aging at 125 degC are correlated with cross-sectional analysis of the solder joints. The mean number of drops to failure decreases by approximately 80% with aging at 125 degC through 480 h. Voids develop at the Cu-Sn intermetallic-to-Cu interface during high-temperature aging, but the crack path is through the intermetallic layer and does not propagate from void-to-void. Thus, it can be concluded that the voids do not contribute to the decrease in drop test survivability observed in this study     

Degradation of thermal interface materials for high-temperature power electronics applications

The specific thermal resistance values of several thermal interface materials (TIMs) intended to thermally enhance Cu contact pairs and their degradation under isothermal ageing at 170 °C have been investigated using Cu stack samples consisting of 10 Cu discs and 9 layers of the TIMs. The results obtained indicate that the specific thermal resistance values of the as-prepared Cu stack samples, one with conductive Ag thermal grease, one with Sn–3.5Ag solder joints and one with 25 μm thick Sn foil as TIMs are significantly lower than those of the Cu stack sample without any TIM. However, after the isothermal ageing at 170 °C for 90 days, the specific thermal resistance values of the samples with these TIMs are not substantially different from those of the sample without any TIM. Also reported in this paper is an estimation of testing errors for the specific thermal resistance values, microstructure characterization of the aged samples and effect of the degradation of these TIMs on the thermal performance of a high-temperature half bridge power switch module.     

Reliability of large periphery GaN-on-Si HFETs

GaN devices exhibit excellent potential for use in many RF applications. However, commercial acceptance of the technology has been hindered by the scarcity and non-statistical nature of reliability results. In this work we present a full device level reliability study of GaN-on-Si HFETs. Reliability results on this technology include three-temperature DC data that show an activation energy of 1.7 eV and an average failure time >10⁷ h at 150 °C. Additionally, long duration DC lifetest (30 000 device hours) and RF lifetest (4000 device hours) results demonstrate a repeatable low drift process. Environmental tests such as autoclave and ESD demonstrate the ruggedness of the material system and technology. Finally, initial failure analysis is discussed.     

To Your Health: Self‐Regulation of Health Behavior Through Selective Exposure to Online Health Messages

Reaching target audiences is of crucial importance for the success of health communication campaigns, but individuals may avoid health messages if they challenge their beliefs or behaviors. A lab study (N = 419) examined effects of messages' consistency with participants' behavior and source credibility on selective exposure for 4 health lifestyle topics. Drawing on self‐regulation theory and dissonance theory, 3 motivations were examined: self‐bolstering, self‐motivating, and self‐defending. Prior behavior predicted selective exposure across topics, reflecting self‐bolstering. Standard‐behavior discrepancies also affected selective exposure, consistent with self‐motivating rather than self‐defending. Selective exposure to high‐credibility sources advocating for organic food, fruits and vegetable consumption, exercise, and limiting coffee all fostered accessibility of related standards, whereas messages from low‐credibility sources showed no such impact.     

Impact of the injection‐level‐dependent lifetime on Voc,FF, ideality m,J02, and the dim light response in a commercial PERC cell

The injection‐level‐dependent (ILD) lifetime of the silicon wafer impacts many characteristics of the final photovoltaic cell. While efficiency is commonly understood to be impacted by the silicon bulk lifetime (at the maximum power point injection level), this work demonstrates the wide ranging impacts of ILD lifetime on the V_oc, the fill factor (FF), the diode ideality factor m, and the dim light response. Instead of a two‐diode model, we utilize a boundary + ILD bulk lifetime model to analyze a commercial passivated emitter rear contact (PERC) cell featuring an AlO_x dielectric rear passivation. The ILD lifetime is directly measured and used to calculate the bulk recombination current across injection levels. With this boundary + ILD lifetime model, we demonstrate the role of the ILD lifetime on many cell parameters in this PERC cell. For most high efficiency commercial p‐type monocrystalline solar cells, the typically lower bulk lifetime at the maximum power point versus the lifetime at the open circuit point reduces the measured FF and pseudo‐FF. This work illustrates that for a commercial PERC cell with AlO_x rear passivation, the ILD lifetime is the primary mechanism behind reduced FF, ideality factors greater than 1, and the source of the J₀₂ term in the two‐diode model. The crucial implications of this work are not only to better understand commercial PERC cell loss mechanisms but also to encourage a focus on different metrics in cell diagnostics. One such metric is the V_oc at 0.1 or 0.05 suns. Copyright © 2016 John Wiley & Sons, Ltd.     

HF chemical etching of SiO2 on 4H and 6H SiC

Thickness and etch rate of SiO₂ films thermally grown on hexagonal SiC substrates were compared to results obtained from SiO₂/Si samples. The data confirm that profilometry and ellipsometry yield the same thickness values for oxides grown on Si and SiC. Within the accuracy of our measurements, oxides grown on different polytypes and faces of SiC etch at the same rate in a HF acid solution. The etch rate using a 50:1 H₂O:HF(50%) solution at room temperature is 0.1 nm/s and is uniform throughout the thickness of the SiO₂ films. The rate is the same as that obtained for SiO₂ grown on Si.     

采用MUF的倒装芯片封装技术

业界对信号完整性和电学性能提出了越来越高的要求,因而开始向更薄基板的方向发展,Amkor Technology Inc.开发出一种使用模塑底部填充（MUF）而非毛细底部填充（CUF）的倒装芯片模塑球栅阵列（FCMBGA）封装技术,使得无源器件与倒装芯片的间距更小,同时还提供了更优的薄芯基板变形控制,并可以获得更好的焊料连接可靠性。