Design and Architecture of Low‐Latency High‐Speed Turbo Decoders

In this paper, we propose and present implementation results of a high‐speed turbo decoding algorithm. The latency caused by (de)interleaving and iterative decoding in a conventional maximum a posteriori turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is from the combination of the radix‐4, center to top, parallel decoding, and early‐stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real‐time wireless communication services. The proposed scheme results in a slight degradation in bit error rate performance for large block sizes because the effective interleaver size in a radix‐4 implementation is reduced to half, relative to the conventional method. To prove the latency reduction, we implemented the proposed scheme on a field‐programmable gate array and compared its decoding speed with that of a conventional decoder. The results show an improvement of at least five fold for a single iteration of turbo decoding.     

Effects of Interfacial Dielectric Layers on the Electrical Performance of Top‐Gate In‐Ga‐Zn‐Oxide Thin‐Film Transistors

We investigate the effects of interfacial dielectric layers (IDLs) on the electrical properties of top‐gate In‐Ga‐Zn‐oxide (IGZO) thin film transistors (TFTs) fabricated at low temperatures below 200°C, using a target composition of In:Ga:Zn = 2:1:2 (atomic ratio). Using four types of TFT structures combined with such dielectric materials as Si₃N₄ and Al₂O₃, the electrical properties are analyzed. After post‐annealing at 200°C for 1 hour in an O₂ ambient, the sub‐threshold swing is improved in all TFT types, which indicates a reduction of the interfacial trap sites. During negative‐bias stress tests on TFTs with a Si3N4 IDL, the degradation sources are closely related to unstable bond states, such as Si‐based broken bonds and hydrogen‐based bonds. From constant‐current stress tests of Id = 3 µA, an IGZO‐TFT with heat‐treated Si₃N₄ IDL shows a good stability performance, which is attributed to the compensation effect of the original charge‐injection and electron‐trapping behavior.     

An improved sensorless driving method for SRM using a phase-shift circuit technique

This paper presents an improved sensorless driving method for switched reluctance motor (SRM) using a phase-shift circuit technique. The conventional method consists of impressing short voltage pulses during unenergized phases, measuring the phase current pulses, and finding the correlation between the filtered current signals and rotor position. However, the filtering process causes a signal phase delay which varies with motor speed. This delay must be compensated for in providing the sensorless signal which is proper to the rotor position. A solution for this phase delay compensation, based on a simple analog and digital circuit, is proposed in this paper.     

Phase-separated polydimethylsiloxane as a dielectric surface treatment layer for organic field effect transistors

We suggest a novel method for treating the surfaces of dielectric layers in organic field effect transistors (OFETs). In this method, a blend of poly(9,9-dioctylfluorene-alt-bithiophene) (F8T2) and dimethylsiloxane (DMS) with a curing agent is spin coated onto the surface of a dielectric substrate, silicon oxide (SiO₂), and then thermally cured. X-ray photoelectron spectroscopy, contact angle measurements, and morphology analysis were used to show that the hydrophilic DMS layer is preferentially adsorbed on the SiO₂ substrate during the spin coating process. After thermal curing, the bottom DMS layer becomes a hydrophobic PDMS layer. This bottom PDMS layer becomes thinner during curing due to the upward motion of the hydrophobic PDMS molecules. The FET mobility of the cured system was 10^?2 cm²/Vs, which is similar to that of polymeric semiconductors on octadecyltrichlorosilane treated SiO₂ dielectric layers. We also discuss the possibility of using this blend method to increase the air-stability of polymeric semiconductors.     

Determination of the interface energy level alignment of a doped organic hetero-junction using capacitance–voltage measurements

A simple method based on capacitance–voltage (C–V) measurements is reported to determine the interface energy level alignment at the junction of 15 mol% Cs₂CO₃ doped 4,7-diphenyl-1,10-phenanthroline (BPhen) and 1,4,5,8,9,11-hexaazatriphenylene hexacarbonitrile (HATCN) fabricated under high vacuum. The junction properties, such as the depletion layer thickness, built-in potentials and vacuum level shift were calculated with simple Mott–Schottky and Poisson’s equations with the boundary condition of a continuous electric flux density using the information from the C–V data. The interface energy level alignment determined by this method is well matched with the one determined using the in situ ultraviolet photoemission spectroscopy (UPS) and X-ray photoemission spectroscopy (XPS) experiments performed under ultra-high vacuum. This method can be applied to other semiconductor junctions such as the organic p–n homojunctions and heterojunctions with known energy levels, as long as the metal/semiconductor contact is Ohmic without referring to the photoemission spectroscopies. Moreover, the energy level alignment determined by the C–V measurement gives a more realistic result since the films for the measurements are formed under high vacuum which is a normal device fabrication environment rather than under ultra high vacuum.     

Symbiotic Dynamic Memory Balancing for Virtual Machines in Smart TV Systems

Smart TV is expected to bring cloud services based on virtualization technologies to the home environment with hardware and software support. Although most physical resources can be shared among virtual machines (VMs) using a time sharing approach, allocating the proper amount of memory to VMs is still challenging. In this paper, we propose a novel mechanism to dynamically balance the memory allocation among VMs in virtualized Smart TV systems. In contrast to previous studies, where a virtual machine monitor (VMM) is solely responsible for estimating the working set size, our mechanism is symbiotic. Each VM periodically reports its memory usage pattern to the VMM. The VMM then predicts the future memory demand of each VM and rebalances the memory allocation among the VMs when necessary. Experimental results show that our mechanism improves performance by up to 18.28 times and reduces expensive memory swapping by up to 99.73% with negligible overheads (0.05% on average).     

Impedance-matching arrangement for microwave transponder operating over plurality of bent installations of antenna

An impedance-matching arrangement is considered for an essentially flexible RFID transponder that can operate over a plurality of its bent installations. The novel structure matches the actual complex impedance of the transponder's application-specific integrated circuit to the input impedance of the antenna over different forms of mechanical deformation and thereby improves overall performances of the passive identification system.     

Low-noise amplifier design for ultrawideband radio

A new theoretical approach for designing a low-noise amplifier (LNA) for the ultra-wideband (UWB) radio is presented. Unlike narrow-band systems, the use of the noise figure (NF) performance metric becomes problematic in UWB systems because of the difficulty in defining the signal-to-noise ratio (SNR). By defining the SNR as the matched filter bound (MFB), the NF measures the degree of degradation caused by the LNA in the achievable receiver performance after the digital decoding process. The optimum noise matching network that minimizes the NF as defined above has been solved. When the narrow-band LNA assumption is made, the proposed optimum matching network simplifies to the published optimum narrow-band matching network, and the corresponding NF value also becomes equivalent. Since realizing the optimum matching network is in general difficult, an approach for designing a practical but suboptimum matching network is also presented.     

Enhanced Optical Properties and Stability of CsPbBr3 Nanocrystals Through Nickel Doping

To improve the quantum efficiency and stability of perovskite quantum dots, the structural and optical properties are optimized by varying the concentration of Ni doping in CsPbBr₃ perovskite nanocrystals (PNCs). As Ni doping is gradually added, a blue shift is observed at the photoluminescence (PL) spectra. Ni-doped PNCs exhibit stronger light emission, higher quantum efficiency, and longer lifetimes than undoped PNCs. The doped divalent element acts as a defect in the perovskite structure, reducing the recombination rate of electrons and holes. A stability test is used to assess the susceptibility of the perovskite to light and moisture. For ultra-violet light irradiation, the PL intensity of undoped PNCs decreases by 70%, whereas that of Ni-doped PNCs decreases by 18%. In the water addition experiment, the PL intensity of Ni-doped PNCs is three times that of undoped PNCs. For CsPbBr₃ and Ni:CsPbBr₃ PNCs, a light emitting diode is fabricated by spin-coating. The efficiency of Ni:CsPbBr₃ exceeds that of CsPbBr₃ PNCs, and the results significantly differ based on the ratio. A maximum luminance of 833 cd m^–2 is obtained at optimum efficiency (0.3 cd A^–1). Therefore, Ni-doped PNCs are expected to contribute to future performance improvements in display devices.