System-level reliability assessment of mixed-signal convergent microsystems

The next-generation convergent microsystems, based on system-on-package (SOP) technology, require up-front system-level design-for-reliability approaches and appropriate reliability assessment methodologies to guarantee the reliability of digital, optical, and radio frequency (RF) functions, as well as their interfaces. Systems approach to reliability requires the development of: i) physics-based reliability models for various failure mechanisms associated with digital, optical, and RF Functions, and their interfaces in the system; ii) design optimization models for the selection of suitable materials and processing conditions for reliability, as well as functionality; and iii) system-level reliability models understanding the component and functional interaction. This paper presents the reliability assessment of digital, optical, and RF functions in SOP-based microsystems. Upfront physics-based design-for-reliability models for various functional failure mechanisms are presented to evaluate various design options and material selection even before the prototypes are made. Advanced modeling methodologies and algorithms to accommodate material length scale effects due to enhanced system integration and miniaturization are presented. System-level mixed-signal reliability is discussed thorough system-level reliability metrics relating component-level failure mechanisms to system-level signal integrity, as well as statistical aspects.     

Principal ratio combining for fixed wireless applications whentransmitter diversity is employed

We present a near-optimal detection method for decoding codes appropriate to transmission using multiple transmit antennas in a fixed wireless environment. The method is a nontrivial generalization of maximum ratio combining. This reduces the decoding complexity at the expense of some sacrifice in performance     

Post-stress interface trap generation induced by oxide-field stresswith FN injection

Interface trap generation in nMOS transistors during both stressing and post-stress periods under the conditions of oxide field (dynamic and dc) stress with FN injection is investigated with charge pumping technique. In contrast to the post-stress interface trap generation induced by hot carrier stress which is a logarithmical function of post-stress time, the post-stress interface trap generation induced by oxide-field stress with FN injection first increases with post-stress time but then becomes saturated. The mechanisms for the interface trap generation in both stressing and post-stress periods are described     

Fast clustering process for vector quantisation codebook design

A fast clustering process is introduced to the generalised Lloyd algorithm for vector quantisation codebook design. Simulations show that the proposed codebook design method achieves significant saving in computational time and similar qualitative performance to that of the conventional full-search approach     

Publicly verifiable authenticated encryption

Ma and Chen [2003] have proposed an authenticated encryption scheme with public verifiability. The scheme claims that the TTP can publicly verify the sender's signature without running a zero knowledge proof protocol. The problem in verification which causes the TTP to reject a valid signature with non-negligible probability is pointed out.     

A Wide Tuning Range Gm –C Continuous-Time Analog Filter

A CMOS operational transconductance amplifier (OTA) for low-power and wide tuning range filter application is proposed in this paper. The OTA can work from the weak inversion region to the strong inversion region to maximize the transconductance tuning range. The transconductance can be tuned by changing its bias current. A fifth-order Elliptic low-pass filter implemented with the OTAs was integrated by TSMC 0.18-mum CMOS process. The filter can operate with the cutoff frequency of 250 Hz to 1 MHz. The wide tuning range filter would be suitable for multi-mode applications, especially under the consideration of saving chip areas. The third-order inter-modulation (IM3) of -40 dB was measured over the tuning range with two tone input signals. The power consumption is 0.8 mW at 1-MHz cutoff frequency and 1.8-V supply voltage with the active area less than 0.3 mm²     

A Light‐Blue Phosphorescent Dendrimer for Efficient Solution‐Processed Light‐Emitting Diodes

We describe the preparation of a dendrimer that is solution‐processible and contains 2‐ethylhexyloxy surface groups, biphenyl‐based dendrons, and a fac‐tris[2‐(2,4‐difluorophenyl)pyridyl]iridium(III ) core. The homoleptic complex is highly luminescent and the color of emission is similar to the heteroleptic iridium(III ) complex, bis[2‐(2,4‐difluorophenyl)pyridyl]picolinate iridium(III ) (FIrpic). To avoid the change in emission color that would arise from attaching a conjugated dendron to the ligand, the conjugation between the dendron and the ligand is decoupled by separating them with an ethane linkage. Bilayer devices containing a light‐emitting layer comprised of a 30 wt.‐% blend of the dendrimer in 1,3‐bis(N‐carbazolyl)benzene (mCP) and a 1,3,5‐tris(2‐N‐phenylbenzimidazolyl)benzene electron‐transport layer have external quantum and power efficiencies, respectively, of 10.4 % and 11 lm W^–1 at 100 cd m^–2 and 6.4 V. These efficiencies are higher than those reported for more complex device structures prepared via evaporation that contain FIrpic blended with mCP as the emitting layer, showing the advantage of using a dendritic structure to control processing and intermolecular interactions. The external quantum efficiency of 10.4 % corresponds to the maximum achievable efficiency based on the photoluminescence quantum yield of the emissive film and the standard out‐coupling of light from the device.     

Parasitic extraction: current state of the art and future trends

With the increase in circuit performance (higher speeds) and density (smaller feature size) in deep submicrometer (DSM) designs, interconnect parasitic effects are increasingly becoming more important. This paper first surveys the state of the art in parasitic extraction for resistance, capacitance, and inductance. The paper then covers other related issues such as interconnect modeling, model order reduction, delay calculation, and signal integrity issues such as crosstalk. Some future trends on parasitic extraction, model reduction and interconnect modeling are discussed and a fairly complete list of references is given     

On-line monitoring of partial discharges on stator windings oflarge rotating machines in the petrochemical environment

This paper describes a joint collaboration program between a major large electric machine manufacturer and a petrochemical manufacturer to investigate the effectiveness of time- and frequency-domain techniques for the online monitoring of the health of high-voltage machine stator insulation systems. Information is given on the factory and site testing carried out, as well as on the analysis and discussion of the results. It is concluded that both techniques can be used in the petrochemical environment for general assessments, but the time domain technique is required if identification of specific locations of discharge sites is needed