Unified Systolic-Like Architecture for DCT and DST Using Distributed Arithmetic

A common computing-core representation of the discrete cosine transform and discrete sine transform is derived and a reduced-complexity algorithm is developed for computation of the proposed computing-core. A parallel architecture based on the principle of distributed arithmetic is designed further for the computation of these transforms using the common-core algorithm. The proposed scheme not only leads to a systolic-like regular and modular hardware for computing these transforms, but also offers significant improvement in area-time efficiency over the existing structures. The structure proposed here is devoid of complicated input/output mapping and does not involve any complex control. Unlike the convolution-based structures, it does not restrict the transform length to be a prime or multiple of prime and can be utilized as a reusable core for cost-effective, memory-efficient, high-throughput implementation of either of these transforms     

An optically clocked transistor array with dual serial-to-parallel and parallel-to-serial conversion capability for optical label swapping

We propose an optically clocked transistor array optoelectronic integrated circuit (OEIC) for both serial-to-parallel and parallel-to-serial conversion (demux/mux), enabling an interface between high-speed asynchronous burst optical labels and CMOS circuitry for optical label swapping. Dual functionality of the OEIC reduces size, power, and cost of the optical label swapper. The capability for greater than 20-Gb/s conversion operation is demonstrated.     

Operating Penalties in Single-Fiber Operation 10-Gb/s, 1024-Way Split, 110-km Long-Reach Optical Access Networks

We report for the first time optical signal-to-noise penalties which lead to performance degradations in single-fiber long-reach optical access networks when compared to identical dual-fiber systems. A simplified architecture, with reduced optical amplifier count compared to previous work, for single-fiber operation of a symmetrical 10-Gb/s, 1024-way split, 110-km long-reach optical access network is presented and demonstrated. In addition, a possible solution to remove the optical signal-to-noise penalty is suggested     

A multigrid accelerated hybrid unstructured mesh method for 3D compressible turbulent flow

 A cell vertex finite volume method for the solution of steady compressible turbulent flow problems on unstructured hybrid meshes of tetrahedra, prisms, pyramids and hexahedra is described. These hybrid meshes are constructed by firstly discretising the computational domain using tetrahedral elements and then by merging certain tetrahedra. A one equation turbulence model is employed and the solution of the steady flow equations is obtained by explicit relaxation. The solution process is accelerated by the addition of a multigrid method, in which the coarse meshes are generated by agglomeration, and by parallelisation. The approach is shown to be effective for the simulation of a number of 3D flows of current practical interest. Sponsored by The Research Council of Norway, project number 125676/410 Dedicated to the memory of Prof. Mike Crisfield, a respected colleague     

Catalytic aminolysis of epoxide by alumina prepared from amine-protected Al precursor

The catalytic activities of alumina prepared from an Al alkoxide-amine adduct monomer for the reaction of cyclopentene oxide with piperidine was determined after various pretreatments, including calcination and exposure to moisture. They were compared with the activity of alumina prepared by the conventional hydrolysis method. It was found that the as-prepared sample from the alkoxide-amine monomer preparation was five times more active than a conventional preparation, suggesting that it has a higher density of surface Lewis acid sites. However, its activity was much more severely suppressed by exposure to moisture.     

A decision support system for interactive decision making - Part II: analysis and output interpretation

For pt.I see ibid., p.42-55 (2003). The development of a comprehensive decision support system, GMCR II, for the systematic study of real-world interactive decision problems is presented. The companion paper (Part I), discusses how GMCR II elicits, stores, and manages conflict models; here (Part II), the focus is on GMCR IIs analysis and output interpretation subsystems. Specifically, this paper describes the powerful and efficient analysis engine contained in GMCR II, its informative output presentation and interpretation facilities, and a number of follow-up analyses. Furthermore, an illustrative case study is used to demonstrate how GMCR II can be conveniently applied in practice.     

A Method to Measure Emissions from Dryers with Diffuse Leakages, Using Evaporated Water as a Tracer

This paper describes a novel method to measure emission from dryers. The method resolves the known difficulties caused by diffuse emissions, and also solves the problems associated with high moisture content of the drying medium. The basic idea is to use water vapor to determine the exhaust flow, while a dry ice trap is used both to preconcentrate emitted VOCs and to determine the moisture content of the drying medium.     

Exposed Die-Top Encapsulation Molding for an Improved High- Performance Flip Chip BGA Package

The recent advancement in high- performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip ball grid array (BGA) package with high pin count and targeted reliability has emerged as a popular choice. The flip chip technology can accommodate an I/O count of more than five hundreds500, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. None the less, greater expectations on these high-performance packages arose such as better substrate real estate utilization for multiple chips, ease in handling for thinner core substrates, and improved board- level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planar top surface can be formed. A, and a flat lid can then be mounted on the planar mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multichip package and thin core substrate options. Finite-element simulations have been employed for the study of its structural integrity, thermal, and electrical performances. Detailed package and board-level reliability test results will also be reported