全文获取类型
收费全文 | 14025篇 |
免费 | 762篇 |
国内免费 | 43篇 |
专业分类
电工技术 | 170篇 |
综合类 | 15篇 |
化学工业 | 2616篇 |
金属工艺 | 451篇 |
机械仪表 | 940篇 |
建筑科学 | 229篇 |
矿业工程 | 3篇 |
能源动力 | 438篇 |
轻工业 | 1101篇 |
水利工程 | 83篇 |
石油天然气 | 14篇 |
无线电 | 2347篇 |
一般工业技术 | 2745篇 |
冶金工业 | 2068篇 |
原子能技术 | 167篇 |
自动化技术 | 1443篇 |
出版年
2024年 | 6篇 |
2023年 | 155篇 |
2022年 | 169篇 |
2021年 | 436篇 |
2020年 | 283篇 |
2019年 | 326篇 |
2018年 | 369篇 |
2017年 | 420篇 |
2016年 | 457篇 |
2015年 | 379篇 |
2014年 | 554篇 |
2013年 | 827篇 |
2012年 | 833篇 |
2011年 | 1016篇 |
2010年 | 735篇 |
2009年 | 781篇 |
2008年 | 723篇 |
2007年 | 569篇 |
2006年 | 494篇 |
2005年 | 448篇 |
2004年 | 415篇 |
2003年 | 371篇 |
2002年 | 383篇 |
2001年 | 293篇 |
2000年 | 261篇 |
1999年 | 281篇 |
1998年 | 746篇 |
1997年 | 463篇 |
1996年 | 345篇 |
1995年 | 201篇 |
1994年 | 187篇 |
1993年 | 156篇 |
1992年 | 83篇 |
1991年 | 80篇 |
1990年 | 71篇 |
1989年 | 65篇 |
1988年 | 44篇 |
1987年 | 62篇 |
1986年 | 32篇 |
1985年 | 43篇 |
1984年 | 16篇 |
1983年 | 11篇 |
1982年 | 20篇 |
1981年 | 21篇 |
1980年 | 16篇 |
1979年 | 3篇 |
1978年 | 7篇 |
1977年 | 53篇 |
1976年 | 110篇 |
1973年 | 4篇 |
排序方式: 共有10000条查询结果,搜索用时 109 毫秒
991.
The aim of this research was to develop a usability evaluation model based on customer sensation using quality function deployment (QFD), which evaluates the relationship between consumer sensation and usability among the physical design factors of dishwashers. Four aspects of the evaluation model were analyzed with QFD: overall sensation factors, detail sensation factors, usability evaluation factors, and physical design factors of products in 3 sequential processes. The sensation evaluation factors and the usability evaluation factors were created from the results of the sensation and usability tests. Moreover, experts and manufacturers were involved in selecting the physical design factors. With the evaluation model using these 4 aspects, physical design factors influencing user sensation were generated. These factors were Label Icon, Rack Size, Shape of Knob, and LCD size. In addition, the degree of influences was tested and design guidelines derived from the final physical design factors were generated. © 2009 Wiley Periodicals, Inc. 相似文献
992.
The effect of tris(methoxy diethylene glycol) borate (TMDGB) on the coordination structure between ethylene carbonate (EC) solvents with high permittivity and ClO4− anions has been investigated by using a Fourier transform infrared (FT-IR) spectroscopy. The results of FT-IR analyses manifested that the boron atom of TMDGB anion receptor forms the complex with ClO4− anions. Even though Lewis acid-base interaction between the TMDGB anion receptor and ClO4− anions in the electrolyte solution lead to the prominent enhancement of both the dissociation degree of lithium salts and the lithium ion transference number, the ionic conductivity of the EC-based electrolyte solution decreased due to the trap of ClO4− anions by introducing the TMDGB anion receptor.The electrochemical stability of gel polymer electrolyte based on semi-interpenetrating network (IPN) structure with tris(pentafluoro phenyl) borane (TPFPB) or TMDGB anion receptor was obviously improved. 相似文献
993.
We evaluate a closed form expression of the transition probabilities used for calculating metric values and pairwise error probabilities of convolutional codes, equipped with coherent BPSK signals, for hard-decision decoding with k-bit channel state information (CSI) in slow varying frequency nonselective Nakagami-m fading channels. It is noted that 1-bit CSI is sufficient to take advantage of channel information under deep fadings 相似文献
994.
High-frequency components of leakage current as diagnostic tool to study aging of polymer insulators under salt fog 总被引:1,自引:0,他引:1
The results of using the high-frequency components of the leakage current to study aging of contaminated insulators under salt fog conditions. Experimental results demonstrate that the high-frequency components can be used effectively to study aging of polymer insulators in a salt fog test. 相似文献
995.
A new multi-valued static random access memory (MVSRAM) cell with a hybrid circuit consisting of a single-electron (SE) and MOSFETs is proposed. The previously reported MVSRAM with an SE-MOSFET hybrid circuit needs two data lines, one bit line for write operations and one sense line for read operations, to improve the speed of the read-out operation, but the proposed cell has only one data line for read/write operations, resulting in a memory area that is much smaller than that of the previous cell, without any reduction of read-out speed. 相似文献
996.
997.
Bon Ki Koo Young Kyu Choi Chang Woo Chu Jae Chul Kim Byoung Tae Choi 《ETRI Journal》2005,27(2):235-238
A new mesh reconstruction scheme for approximating a surface from a set of unorganized 3D points is proposed. The proposed method, called a shrink‐wrapped boundary face (SWBF) algorithm, produces the final surface by iteratively shrinking the initial mesh generated from the definition of the boundary faces. SWBF surmounts the genus‐0 spherical topology restriction of previous shrink‐wrapping‐based mesh generation techniques and can be applied to any type of surface topology. Furthermore, SWBF is significantly faster than a related algorithm of Jeong and others, as SWBF requires only a local nearest‐point‐search in the shrinking process. Our experiments show that SWBF is very robust and efficient for surface reconstruction from an unorganized point cloud. 相似文献
998.
999.
1000.
Nakase Y. Morooka Y. Perlman D.J. Kolor D.J. Jae-Myoung Choi Shin H.J. Yoshimura T. Watanabe N. Matsuda Y. Kumanoya M. Yamada M. 《Solid-State Circuits, IEEE Journal of》1999,34(4):494-501
This paper describes a validation system for an SLDRAM interface. The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style. The first technique is a source-synchronization scheme. Since the chip that transmits data also supplies the data clock, the clock and data are completely synchronous. The second is the timing vernier technique. A wait time for output data is programmable in each SLDRAM. Therefore, the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size. The validation chip is designed to emulate these operations. The chip is fabricated using a 0.35-μm CMOS process technology and packaged in a conventional 0.65-mm pitch thin small out-line package, mounted on a single-chip module, and put into an eight-module system. A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals. From system-level measurements, the data eye width of 600 ps is obtained at a data rate of 600 Mbps. Errorless data transmission is observed in both read and write operations in a bit-error rate testing. The validation system has successfully demonstrated a data-transmission rate of 1.2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2.5 V 相似文献