Short-channel MOSFETs with oxynitride gate dielectrics fabricated using multiple rapid thermal processing

Short-channel MOSFETs with superior thin gate dielectrics have been successfully fabricated using multiple reactive rapid thermal processing of thermal oxides. The gate dielectrics are produced by rapid thermal nitridation (RTN) of thin thermal oxides in pure NH/sub 3/ ambient followed by rapid thermal reoxidation (RTO) in O/sub 2/ ambient. Devices fabricated with RTO/RTN gate dielectrics exhibit improved hot electron induced degradation compared to those fabricated with pure oxides. In addition, the subthreshold leakage current level of RTO/RTN devices is as good as for standard oxide devices.<>     

The impact of TiN capping Layer on NiSi, CoSi/sub 2/, and Co/sub x/Ni/sub 1-x/Si/sub 2/ FUSI metal gate work function adjustment

The impact of TiN capping layer on dual work functions of Ni, Co, and Co-Ni fully silicided (FUSI) metal gates was investigated. It was found that the TiN capping layer significantly altered the distribution of both n- and p-dopants during the FUSI process, which in turn changed the work functions of both As-doped and B-doped in the three FUSI metal gate systems. The work function tuning was found to have a linear relationship with the change of dopant level at the silicides/dielectric interface after adding TiN capping layer. The investigation of TiN capping layer on FUSI provided some insights on work function tuning mechanism in FUSI systems. This work also suggested a new methodology for optimizing the nMOS and pMOS work functions for CMOS device applications.     

Novel gate voltage ramping technique for the characterisation of metal-oxide-semiconductor capacitor charge trapping properties

A novel technique is proposed to characterise the charge trapping properties of MOS capacitors by using the gate voltage ramping test. The parameter I=1-I/sub g/(t)/I/sub s/(t+ Delta t) measured during gate voltage ramping reveals the dielectric charge trapping characteristics. Positive charge trapping before dielectric breakdown was observed using this technique. A comparison between I and flatband voltage shift, Delta V/sub fb/, indicates that I gives the same information as Delta V/sub fb/ does at high stress fluences.<>     

Investigation of hole-tunneling current through ultrathinoxynitride/oxide stack gate dielectrics in p-MOSFETs

The systematic investigation of hole tunneling current through ultrathin oxide, oxynitride, oxynitride/oxide (N/O) and oxide/oxynitride/oxide (ONO) gate dielectrics in p-MOSFETs using a physical model is reported for the first time. The validity of the model is corroborated by the good agreement between the simulated and experimental results. Under typical inversion biases (|VG|<2 V), hole tunneling current is lower through oxynitride and oxynitride/oxide with about 33 at.% N than through pure oxide and nitride gate dielectrics. This is attributed to the competitive effects of the increase in the dielectric constant, and hence dielectric thickness, and decrease in the hole barrier height at the dielectric/Si interface with increasing with N concentration for a given electrical oxide thickness (EOT). For a N/O stack film with the same N concentration in the oxynitride, the hole tunneling current decreases monotonically with oxynitride thickness under the typical inversion biases. For minimum gate leakage current and maintaining an acceptable dielectric/Si interfacial quality, an N/O stack structure consisting of an oxynitride layer with 33 at.% N and a 3 Å oxide layer is proposed. For a p-MOSFET at an operating voltage of -0.9 V, which is applicable to the 0.7 μm technology node, this structure could be scaled to EOT=12 Å if the maximum allowed gate leakage current is 1 A/cm² and EOT=9 Å if the maximum allowed gate leakage current is 100 A/cm²     

Interface trap passivation effect in NBTI measurement for p-MOSFET with SiON gate dielectric

New findings of interface trap passivation effect in negative bias temperature instability (NBTI) measurement for p-MOSFETs with SiON gate dielectric are reported. We show evidence to clarify the recent debate: the recovery of V/sub th/ shift in the passivation phase of the dynamic NBTI is mainly due to passivation of interface traps (N/sub it/), not due to hole de-trapping in dielectric hole traps (N/sub ot/). The conventional interface trap measurement methods, dc capacitance-voltage and charge pumping, seriously underestimate the trap density N/sub it/. This underestimation is gate bias dependent during measurement, because of the accelerated interface trap passivation under positive gate bias. Due to this new finding, many of previous reliability studies of p-MOSFETs should be re-investigated.     

Study of Ta-barrier and pore sealing dielectric layer interaction for enhanced barrier performance of Cu/ultralow /spl kappa/(/spl kappa/<2.2) interconnects

For Cu/ultralow /spl kappa/ application, understanding of interfacial interaction between Ta and pore-sealing layer over porous dielectric is very important in order to achieve a good barrier performance. However, characterizing the effect of pore-sealing layer on barrier performance poses a big challenge. Most studies monitored degradation of the electrical performance of the Ta barrier after integration process with little discussions on interfacial interaction. In this letter, the interaction at the interface between Ta and pore-sealing layer deposited over porous SiLK (/spl kappa//spl sim/2.2) film is investigated. The barrier performance is improved significantly by nitrogen incorporation during liner growth. This methodology is very effective for improving metal barrier and pore-sealing performance for Cu/ultralow /spl kappa/ interconnects.     

Fast DNBTI components in p-MOSFET with SiON dielectric

For the first time, we perform a systematic investigation of the fast components of dynamic negative biased temperature instability (DNBTI) in p-MOSFET with an ultrathin SiON gate dielectric. Experimental results unambiguously show a fast DNBTI component measured by a recently developed fast measurement method, and this component is due to trapping and detrapping of hole traps N/sub ot/ in SiON. The cumulative degradation increases with increasing stress frequency. Model simulations are in excellent agreement with all experimental data.     

Integrated high-/spl kappa/ (/spl kappa/ /spl sim/19) MIM capacitor with Cu/low-/spl kappa/ interconnects for RF application

We demonstrate a high-performance metal-high /spl kappa/ insulator-metal (MIM) capacitor integrated with a Cu/low-/spl kappa/ backend interconnection. The high-/spl kappa/ used was laminated HfO/sub 2/-Al/sub 2/O/sub 3/ with effective /spl kappa/ /spl sim/19 and the low-/spl kappa/ dielectric used was Black Diamond with /spl kappa/ /spl sim/2.9. The MIM capacitor (/spl sim/13.4 fF//spl mu/m/sup 2/) achieved a Q-factor /spl sim/53 at 2.5 GHz and 11.7 pF. The resonant frequency f/sub r/ was 21% higher in comparison to an equivalently integrated Si/sub 3/N/sub 4/-MIM capacitor (/spl sim/0.93 fF//spl mu/m/sup 2/) having similar capacitance 11.2 pF. The impacts of high-/spl kappa/ insulator and low-/spl kappa/ interconnect dielectric on the mechanism for resonant frequency improvement are distinguished using equivalent circuit analysis. This letter suggests that integrated high-/spl kappa/ MIM could be a promising alternative capacitor structure for future high-performance RF applications.     

Temperature-modulated fluorescence tomography in a turbid media

High scattering in biological tissues makes fluorescence tomography inverse problem very challenging in thick medium. We describe an approach termed "temperature-modulated fluorescence tomography" that can acquire fluorescence images at focused ultrasound resolution. By utilizing recently emerged temperature sensitive fluorescence contrast agents, this technique provides fluorescence images with high resolution prior to any reconstruction process. We demonstrate that this technique is well suited to resolve small fluorescence targets located several centimeters deep in tissue.