Friction model for friction stir welding process simulation: Calibrations from welding experiments

The accurate 3D finite element simulation of the Friction Stir Welding (FSW) process requires a proper knowledge of both material and interface behaviors, but friction, the key phenomenon of this process, is quite difficult to model and identify. According to the extreme encountered conditions and the highly coupled nature of the material flow, simple tribological tests are not representative enough, so the welding process itself has been utilized in most analyses of the literature, although its complexity has led to use simplified numerical models and approaches. The recent development of more accurate 3D simulation software, which allows modeling the entire complexity of the FSW process, makes it possible to follow a much more rigorous inverse analysis (or calibration) approach. FSW trials are conducted on an Al 6061 aluminum plate with an unthreaded concave tool. Forces and tool temperatures are accurately recorded at steady welding state, for different welding speeds. The numerical simulations are based on an Arbitrary Lagrangian Eulerian (ALE) formulation that has been implemented in the Forge3^® F.E. software. The main feature of the numerical approach is to accurately compute the contact and frictional surface between the plate and the tool. A first study using Norton's friction model show the great sensitivity of welding forces and tool temperatures to friction coefficients, the need to take into account the changes brought to the contact surface by slight friction variations (thanks to the ALE formulation), the possibility to get very accurate calibrations on forces, and the impossibility to properly render the tool temperature profile. On the other hand, the use of Coulomb's friction model allows obtaining realistic temperature profiles and so calibrating a friction coefficient that offers an excellent agreement with experiments, on forces as much as on tool temperatures, for various welding speeds.     

Thermal management of power electronics modules packaged by a stacked-plate technique

The research presented in this paper is part of a multidisciplinary research program of the Center for Power Electronics Systems at Virginia Tech. The program supported by the Office of Naval Research focuses on the development of innovative technologies for packaging power electronics building blocks. The primary objective of this research is to improve package performance and reliability through thermal management, i.e., reducing device temperatures for a given power level. The task of thermal management involves considering trade-offs in the electrical design, package layout and geometry, materials selection and processing, manufacturing feasibility, and production cost. Based on the electrical design of a simple building block, samples of packaged modules, rated at 600 V and 3.3 kW, were fabricated using a stacked-plate technique, termed metal posts interconnected parallel plate structure (MPIPPS). The MPIPPS technique allows the power devices to be interconnected between two direct-bond copper substrates via the use of metal posts. Thermal modeling results on the MPIPPS packaged modules indicate that the new packaging technique offers a superior thermal management means for packaging power electronics modules.     

On the coefficient quantization of the Fourier basis

A family of function bases is devised from a superposition of unit characteristic functions. It is shown that these simple bases can be used to perform a quantized Fourier transform. Furthermore, the transform can be implemented in an iterative scheme such that system resources are balanced in accordance with performance.     

History of the “Detector Materials Engineering” Crystal Growth Process for Bulk Hg1−x Cd x Te

This paper reviews the history and technology of a bulk Hg_1?x Cd _x Te crystal growth process that was developed in the early 1980s at Honeywell Electro-Optics Division (presently BAE Systems, Electronic Solutions). The crystal growth process name, DME, was an acronym for the department name: Detector Materials Engineering. This was an accelerated crucible rotation technique (ACRT) vertical traveling heater method growth process. Crystal growth occurred in the pseudobinary Hg_1?x Cd _x Te system. ACRT mixing allowed the lower-density, higher-x-value Hg_1?x Cd _x Te growth nutrient in the upper region of the ampoule to replenish the depleted melt and allowed the growth of constant-x-value, higher-density Hg_1?x Cd _x Te. The material grown by this research and production growth process yielded single crystals that had improved purity, compositional uniformity, precipitate density, and reproducibility in comparison with solid-state recrystallization and other bulk Hg_1?x Cd _x Te growth techniques. Radial and longitudinal nonuniformities in x-value for Hg_1?x Cd _x Te were reduced to <0.0008/cm. The net electrically active background impurities did not exceed 1 × 10¹⁴ cm^?3. Electron mobilities in excess of 1.5 × 10⁶ cm²/V-s were observed at 77 K. Structural defects of less than 10⁴ cm^?2 were measured. Te precipitates were not observed. As a result of these material improvements, long-wavelength infrared (LWIR) photoconductive devices fabricated from DME material had highly desired performance characteristics.     

Using simulations of reduced precision arithmetic to design a neuro-microprocessor

This article describes some of our recent work in the development of computer architectures for efficient execution of artificial neural network algorithms. Our earlier system, the Ring Array Processor (RAP), was a multiprocessor based on commercial DSPs with a low-latency ring interconnection scheme. We have used the RAP to simulate variable precision arithmetic to guide us in the design of arithmetic units for high performance neurocomputers to be implemented with custom VLSI. The RAP system played a critical role in this study, enabling us to experiment with much larger networks than would otherwise be possible. Our study shows that back-propagation training algorithms only require moderate precision. Specifically, 16b weight values and 8b output values are sufficient to achieve training and classification results comparable to 32b floating point. Although these results were gathered for frame classification in continuous speech, we expect that they will extend to many other connectionist calculations. We have used these results as part of the design of a programmable single chip microprocessor, SPERT. The reduced precision arithmetic permits the use of multiple arithmetic units per processor. Also, reduced precision operands make more efficient use of valuable processor-memory bandwidth. For our moderate-precision fixed-point arithmetic applications, SPERT represents more than an order of magnitude reduction in cost over systems with equivalent performance that use commercial DSP chips.     

Optoelectronic charge coupled device (OECCD) using InP MIScapacitor array

An optoelectronic charge coupled device (OECCD) which is directly compatible with an incident optical signal is proposed. The nonlinear partial differential equation consisting of optical generation and recombination is solved in one dimension using the Crank-Nicolson finite-difference scheme. The charge transfer inefficiency is the main parameter considered for the calculation     

Pentacene-based organic thin-film transistors

Organic thin-film transistors using the fused-ring polycyclic aromatic hydrocarbon pentacene as the active electronic material have shown mobility as large as 0.7 cm²/V-s and on/off current ratio larger than 10⁸; both values are comparable to hydrogenated amorphous silicon devices. On the other hand, these and most other organic TFT's have an undesirably large subthreshold slope. We show here that the large subthreshold slope typically observed is not an intrinsic property of the organic semiconducting material and that devices with subthreshold slope similar to amorphous silicon devices are possible     

Improved RNS FIR filter architectures

A new architecture for implementing finite-impulse response (FIR) filters using the residue number system (RNS) is detailed. The design is based on using a restricted modulus set, with moduli of the form 2/sup n/,2/sup n/-1, and 2/sup n/+1. This does not restrict the modulus set to the common 3 modulus set {2/sup n/-1,2/sup n/,2/sup n/+1}, but any number of pairwise relatively prime moduli of this form, for example, {5,7,17,31,32,33}. Based on a comparison with a 2's complement design, the new RNS design can offer a significant speed improvement. The gain is obtained by using a set of small moduli, selected so as to minimize critical path delay and area. An algorithmic approach is used to obtain full adder based architectures that are optimized for area and delay. The modulus set is optimum based on cost parameters for each modulus. This new architecture presents a practical approach to implementing a fast RNS FIR filter.