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991.
Different hierarchical models in pattern analysis and recognition are proposed, based on occurrence probability of patterns. As an important application of recognizing handprinted characters, three typical kinds of hierarchical models such asM
89-89,M
89-36 andM
36-36 have been presented, accompanied by the computer algorithms for computing recognition rates of pattern parts. Moreover, a comparative study of their recognition rates has been conducted theoretically; and numerical experiments have been carried out to verify the analytical conclusions made. Various hierarchical models deliberated in this paper can provide users more or better choices of pattern models in practical application, and lead to a uniform computational scheme (or code). The recognition rates of parts can be improved remarkably by a suitable hierarchical model. For the modelM
89-36 in which case some of the Canadian standard handprinted characters have multiple occurrence probabilities, the total mean recognition rates of the given sample may reach 120% of that by the model proposed by Li et al., and 156% of that obtained from the subjective experiments reported by Suen. 相似文献
992.
The bounded disorder file organization proposed by W. Litwin and D.B. Lomet (1987) uses a combination of hashing and tree indexing. Lomet provided an approximate analysis with the mention of the difficulty involved in exact modeling of data nodes, which motivated this work. In an earlier paper (M.V. Ramakrishna and P. Mukhopadhyay, 1988) we provided an exact model and analysis of the data nodes, which is based on the solution of a classical sequential occupancy problem. After summarizing the analysis of data nodes, an alternate file growth method based on repeated trials using universal hashing is proposed and analyzed. We conclude that the alternate file growth method provides simplicity and significant improvement in storage utilization 相似文献
993.
Kieckhafer R.M. Azadmanesh M.H. 《Parallel and Distributed Systems, IEEE Transactions on》1994,5(1):53-63
In a fault-tolerant distributed system, different non-faulty processes may arrive at different values for a given system parameter. To resolve this disagreement, processes must exchange and vote upon their respective local values. Faulty processes may attempt to inhibit agreement by acting in a malicious or “Byzantine” manner. Approximate agreement defines one form of agreement in which the voted values obtained by the non-faulty processes need not be identical. Instead, they need only agree to within a predefined tolerance. Approximate agreement can be achieved by a sequence of convergent voting rounds, in which the range of values held by non-faulty processes is reduced in each round. Historically, each new convergent voting algorithm has been accompanied by ad-hoc proofs of its convergence rate and fault-tolerance, using an overly conservative fault model in which all faults exhibit worst-case Byzantine behavior. This paper presents a general method to quickly determine convergence rate and fault-tolerance for any member of a broad family of convergent voting algorithms. This method is developed under a realistic mixed-mode fault model comprised of asymmetric, symmetric, and benign fault modes. These results are employed to more accurately analyze the properties of several existing voting algorithms, to derive a sub-family of optimal mixed-mode voting algorithms, and to quickly determine the properties of proposed new voting algorithms 相似文献
994.
Weijia Shang O'Keefe M.T. Fortes J.A.B. 《Parallel and Distributed Systems, IEEE Transactions on》1994,5(2):193-204
This paper describes several loop transformation techniques for extracting parallelism from nested loop structures. Nested loops can then be scheduled to run in parallel so that execution time is minimized. One technique is called selective cycle shrinking, and the other is called true dependence cycle shrinking. It is shown how selective shrinking is related to linear scheduling of nested loops and how true dependence shrinking is related to conflict-free mappings of higher dimensional algorithms into lower dimensional processor arrays. Methods are proposed in this paper to find the selective and true dependence shrinkings with minimum total execution time by applying the techniques of finding optimal linear schedules and optimal and conflict-free mappings proposed by W. Shang and A.B. Fortes 相似文献
995.
Malloy B.A. Lloyd E.L. Soffa M.L. 《Parallel and Distributed Systems, IEEE Transactions on》1994,5(5):498-508
A new approach is given for scheduling a sequential instruction stream for execution “in parallel” on asynchronous multiprocessors. The key idea in our approach is to exploit the fine grained parallelism present in the instruction stream. In this context, schedules are constructed by a careful balancing of execution and communication costs at the level of individual instructions, and their data dependencies. Three methods are used to evaluate our approach. First, several existing methods are extended to the fine grained situation. Our approach is then compared to these methods using both static schedule length analyses, and simulated executions of the scheduled code. In each instance, our method is found to provide significantly shorter schedules. Second, by varying parameters such as the speed of the instruction set, and the speed/parallelism in the interconnection structure, simulation techniques are used to examine the effects of various architectural considerations on the executions of the schedules. These results show that our approach provides significant speedups in a wide-range of situations. Third, schedules produced by our approach are executed on a two-processor Data General shared memory multiprocessor system. These experiments show that there is a strong correlation between our simulation results, and these actual executions, and thereby serve to validate the simulation studies. Together, our results establish that fine grained parallelism can be exploited in a substantial manner when scheduling a sequential instruction stream for execution “in parallel” on asynchronous multiprocessors 相似文献
996.
A synchronizer is a compiler that transforms a program designed to run in a synchronous network into a program that runs in an asynchronous network. The behavior of a simple synchronizer, which also represents a basic mechanism for distributed computing and for the analysis of marked graphs, was studied by S. Even and S. Rajsbaum (1990) under the assumption that message transmission delays and processing times are constant. We study the behavior of the simple synchronizer when processing times and transmission delays are random. The main performance measure is the rate of a network, i.e., the average number of computational steps executed by a processor in the network per unit time. We analyze the effect of the topology and the probability distributions of the random variables on the behavior of the network. For random variables with exponential distribution, we provide tight (i.e., attainable) bounds and study the effect of a bottleneck processor on the rate 相似文献
997.
We consider the design problem for a class of discrete-time and continuous-time neural networks. We obtain a characterization of all connection weights that store a given set of vectors into the network, that is, each given vector becomes an equilibrium point of the network. We also give sufficient conditions that guarantee the asymptotic stability of these equilibrium points. 相似文献
998.
We present a method for analyzing the convergence properties of nonlinear dynamical systems yielding second-order bounds on the domain of attraction of an asymptotically stable equilibrium point and on the time of convergence in the estimated domain. We show that under certain conditions on the system, there exists an analytic solution to the corresponding optimization problem. The method is applied in analyzing the dynamics of a neural network model. 相似文献
999.
1000.
Russel B. Miller Isaac M. Horowitz Constantine H. Houpis A. Finley Barfield 《国际强度与非线性控制杂志
》1994,4(1):211-230
》1994,4(1):211-230
Nonlinear quantitative feedback theory (QFT) and pilot compensation techniques are used to design a 2 × 2 flight control system for the YF-16 aircraft over a large range of plant uncertainty. The design is based on numerical input-output time histories generated with a FORTRAN implemented nonlinear simulation of the YF-16. The first step of the design process is the generation of a set of equivalent linear time-invariant (LTI) plant models to represent the actual nonlinear plant. It has been proven that the solution to the equivalent plant problem is guaranteed to solve the original nonlinear problem. Standard QFT techniques are then used in the design synthesis based on the equivalent plant models. A detailed mathematical development of the method used to develop these equivalent LTI plant models is provided. After this inner-loop design, pilot compensation is developed to reduce the pilot's workload. This outer-loop design is also based on a set of equivalent LTI plant models. This is accomplished by modelling the pilot with parameters that result in good handling qualities ratings, and developing the necessary compensation to force the desired system responses. 相似文献