Memoryless block transceivers with minimum redundancy based on Hartley transforms

This paper proposes real linear transceivers employing minimum redundancy, unlike the standard block transceivers that require, at least, L elements of redundancy, where L is the channel order. In all block-based systems, there is an inherent interblock interference (IBI) that can be eliminated by inserting redundancy. For transceivers based on the discrete Fourier transform (DFT), the redundancy induces a circulant channel matrix, allowing superfast implementations. Although it has been known for some time that the minimum redundancy for IBI-free designs of block transceivers is ⌈L/2⌉, only recently practical DFT-based solutions using minimum redundancy were proposed. However, the extension of these solutions to real transforms, such as the discrete Hartley transform (DHT), is not straightforward. The only known solution imposes a symmetry on the channel model that is unlikely to be met in practice. This paper proposes transceivers with practical zero-forcing (ZF) and minimum mean-squared error (MMSE) receivers using DHT, diagonal, and antidiagonal matrices. The resulting systems are asymptotically as simple as orthogonal frequency-division multiplex (OFDM) and single-carrier with frequency-domain (SC-FD) equalization transceivers. In addition, they do not enforce constraints on the channel model. Several computer simulations indicate the higher throughput of the proposals as compared to the standard solutions.     

Integrated structure and control design for mechatronic systems with configuration-dependent dynamics

This paper considers the optimal design of mechatronic systems with configuration-dependent dynamics. An optimal mechatronic design requires that, among the structural and control parameters, an optimal choice has to be made with respect to design specifications in the different domains. Two main challenges are treated in this paper: the non-convex nature of the optimization problem and the difficulty in modeling serial machines with flexible components and their embedded controllers. The optimization problem is treated using the direct design strategy which considers simultaneously structural and control parameters as variables and adopts non-convex optimization algorithms. Linear time-invariant and gain-scheduling PID controllers are addressed. This methodology is exploited for the multi-objective optimization of a pick-and-place assembly robot with a gripper carried by a variable-length flexible beam. The resulting design tradeoffs between system accuracy and control efforts demonstrate the advantage of an integrated design approach for mechatronic systems with configuration-dependent dynamics.     

SDN-based architecture for providing quality of service to high-performance distributed applications

The specification of quality of service (QoS) requirements in most of the existing networks is still challenging. In part, traditional network environments are limited by their high administrative cost, although software-defined networks (SDNs), a newer network paradigm, simplify the management of the whole network infrastructure. In fact, SDN provides a simple way to effectively develop QoS provisioning mechanisms. In this sense, we explore the SDN model and its flexibility to develop a QoS provisioning architecture. Through the use of our new architecture, network operators are able to specify QoS levels in a simple way. Each individual data flow can be addressed, and the architecture we propose also negotiates the QoS requirements between the network controller and applications. On the other hand, the network controller continuously monitors the network environment. Then, it allocates network elements resources and prioritizes traffic, adjusting the network performance. We evaluate the feasibility of our QoS provisioning mechanism by presenting three experimental setups under realistic scenarios. For example, for a given scenario where we evaluate file transfers, our results indicate that the additional SDN modules present negligible overhead. Moreover, for a given setup, we observe a reduction of up to 82% in the file transfer times.     

Proposal and implementation of a new interpolation technique for a double folding A/D converter

This proposal of a new interpolation technique is presented for application in a double folding A/D converter with interpolation. This interpolation technique is applied in the master latches of the A/D converter without consumption increase. Compared to resistive interpolation, this new interpolation technique has the advantage of avoiding the resistive interpolation ladder adding only three transistors in some master latches and the current is the same as in the simple master latch. A 6-bit A/D converter was designed and implemented in a 1.2 μm BiCMOS process, an F_T of 8 GHz, to explain the implementation of interpolation circuitry and evaluate the experimental results.     

Recyclable,Flexible, Low‐Power Oxide Electronics

The ability to process and dimensionally scale field‐effect transistors with and on paper and to integrate them as a core component for low‐power‐consumption analog and digital circuits is demonstrated. Low‐temperature‐processed p‐ and n‐channel integrated oxide thin‐film transistors in the complementary metal oxide semiconductor (CMOS) inverter architecture are seamlessly layered on mechanically flexible, low‐cost, recyclable paper substrates. The possibility of building these circuits using low‐temperature processes opens the door to new applications ranging from smart labels and sensors on clothing and packaging to electronic displays printed on paper pages for use in newspapers, magazines, books, signs, and advertising billboards. Because the CMOS circuits reported constitute fundamental building blocks for analog and digital electronics, this development creates the potential to have flexible form factor computers seamlessly layered onto paper. The holistic approach of merging low‐power circuitry with a recyclable substrate is an important step towards greener electronics.     

ARQ protocols with adaptive block size perform better over a widerange of bit error rates

The throughput of conventional automatic-repeat-request (ARQ) protocols, such as the stop-and-wait, go-back-N, and selective repeat, can be improved by dynamically adapting the protocol block length so that it approaches the optimum value for varying channel bit error rates. A very simple algorithm to implement such an adaptive scheme is presented. The algorithm assumes a known block error rate, estimates the bit error rate, and determines the best block length. Results of a simulation study show that in spite of its simplicity, the algorithm performs well     

Touch‐Interactive Flexible Sustainable Energy Harvester and Self‐Powered Smart Card

Sustainable and safe energy sources combined with cost effectiveness are major goals for society when considering the current scenario of mass production of portable and Internet of Things (IoT) devices along with the huge amount of inevitable e‐waste. The conceptual design of a self‐powered “eco‐energy” smart card based on paper promotes green and clean energy, which will bring the zero e‐waste challenge one step closer to fruition. A commercial raw filter paper is modified through a fast in situ functionalization method, resulting in a conductive cellulose fiber/polyaniline composite, which is then applied as an energy harvester based on a mechano‐responsive charge transfer mechanism through a metal/conducting polymer interface. Different electrodes are studied to optimize charge transfer based on contact energy level differences. The highest power density and current density obtained from such a paper‐based “eco‐energy” smart card device are 1.75 W m^?2 and 33.5 mA m^?2 respectively. This self‐powered smart energy card is also able to light up several commercial light‐emitting diodes, power on electronic devices, and charge capacitors.     

Tree coding of bilevel images

Presently, sequential tree coders are the best general purpose bilevel image coders and the best coders of halftoned images. The current ISO standard, Joint Bilevel Image Experts Group (JBIG), is a good example. A sequential tree coder encodes the data by feeding estimates of conditional probabilities to an arithmetic coder. The conditional probabilities are estimated from co-occurrence statistics of past pixels, the statistics are stored in a tree. By organizing the code length calculations properly, a vast number of possible models (trees) reflecting different pixel orderings can be investigated within reasonable time prior to generating the code. A number of general-purpose coders are constructed according to this principle. Rissanen's (1989) one-pass algorithm, context, is presented in two modified versions. The baseline is proven to be a universal coder. The faster version, which is one order of magnitude slower than JBIG, obtains excellent and highly robust compression performance. A multipass free tree coding scheme produces superior compression results for all test images. A multipass free template coding scheme produces significantly better results than JBIG for difficult images such as halftones. By utilizing randomized subsampling in the template selection, the speed becomes acceptable for practical image coding     

A new programming model for dependable adaptive real-time applications

The CORTEX project envisions a new class of applications comprising (possibly many) smart components, called sentient objects, that can sense their environment and interact with it and each other by accepting and producing events. These interactions might occur in ways that demand predictable and sometimes guaranteed quality of service (QoS). However, achieving predictability is difficult given the objects' changing environments dictated by unstable and mobile object populations, unpredictable network load, varying connectivity, and failed system components. We devised an innovative programming model that aims to reconcile uncertainty with an application's required predictability. The model is based on fulfilling two predicates - coverage stability and no-contamination - by programs or protocols subject to varying conditions of system timeliness.     

Two-step channel selection-a novel technique for reconfigurable multistandard transceiver front-ends

This paper starts with a review of the prevailing channel-selection techniques utilized so far in the design of wireless transceiver analog front-ends before describing a novel two-step channel-selection technique, which handles the traditionally unwanted image, in radio frequency-to-intermediate frequency (RF-to-IF) or IF-to-RF frequency conversion, as a useful adjacent channel of the desired one, and selects deliberately either of them from IF to baseband (or baseband to IF). Thus, one more channel-selection possibility is created for both low-IF receivers and two-step-up transmitters. The consequential benefits of introducing channel selection at IF consist of two. First, many design specifications (such as phase noise and settling time) of the RF frequency synthesizer and local oscillator can be substantially relaxed. Second, a low-IF/zero-IF reconfigurable receiver and a direct-up/two-step-up reconfigurable transmitter can be synthesized to match better with narrowband-wideband-mixed multistandard systems. The operating principles of such architectures are presented in easy-to-understand complex-signal spectral-flow illustrations, and their practicability is demonstrated in the design of a Bluetooth/IEEE 802.11FH/HomeRF multistandard receiver. SPECTRE simulation results validate the reconfigurable functionalities mainly implemented by a triple-mode channel-select filter and a multifunctional sampling-mixer scheme.