Experimental Study of a Thermoelectric Generation System

A flat wall-like thermoelectric generation system is developed for applications in exhaust heat of kilns. The design of the whole experimental setup is presented. The essential performance of the thermoelectric generation system is tested, including open-circuit voltage, output power, and system conversion efficiency. The results illustrate that, when heat source insulation is not considered, the system conversion is efficient at hot-side temperatures between 120°C and 150°C. In addition, the nonuniformity of heat transfer is found to significantly affect the power-generating ability of the system. System-level simulation is carried out using a quasi-one-dimensional numerical model that enables direct comparison with experimental results. The results of both experiment and simulation will provide a foundation to improve and optimize complex thermoelectric generation systems.     

Effect of Electric Current on the Performance of Bi<Subscript>1.2</Subscript>Sb<Subscript>4.8</Subscript>Te<Subscript>9</Subscript> Thermoelectric Material Prepared by a Field-Activated Pressure-Assisted Sintering Process

Field-activated pressure-assisted sintering (FAPAS) was applied to sinter Bi_1.2Sb_4.8Te₉ thermoelectric materials under different conditions, including no-current sintering (NCS), low-density current sintering (LCS), and high-density current sintering (HCS). The effect of the current density on the final thermoelectric performance of the products was investigated. Applying a higher-density electric current and shorter dwell time can improve the thermoelectric performance of the sample by increasing its electric conductivity and decreasing its thermal conductivity. The maximum figure of merit ZT values of the NCS, LCS, and HCS samples were 0.46, 0.48, and 0.57, respectively. Therefore, applying a high-density electric current in the sintering process may be an effective way to obtain Bi_1.2Sb_4.8Te₉ thermoelectric material with high ZT value.     

An Investigation of Diffusion Barrier Characteristics of an Electroless Co(W,P) Layer to Lead-Free SnBi Solder

Diffusion barrier characteristics for eutectic SnBi solder/electroless Co(W,P) couples were investigated via liquid-state aging at 250°C and solid-state aging at 120°C. At the couple interface, CoSn₃ intermetallic compound (IMC) spallation was observed for the SnBi/amorphous Co(W,P) couple subjected to liquid-state aging. In contrast, no spallation of IMCs was observed for the SnBi/amorphous Co(W,P) couples subjected to solid-state aging. For the SnBi/polycrystalline Co(W,P) couple, a thick IMC layer was observed adjacent to a tungsten-enriched amorphous interfacial layer regardless of aging conditions. IMC formation in all samples indicated that Co(W,P) is essentially a sacrificial barrier to SnBi solder. However, amorphous Co(W,P) might also exhibit stuffed-type barrier behavior due to its relatively high phosphorus (P) content. Analytical results indicated that the P content in Co(W,P) is a crucial factor affecting the structural evolution at the SnBi/electroless Co(W,P) interface.     

Structural Test Approach for Embedded Analog Circuits Based on a Built-in Current Sensor

This paper presents a test method based on the analysis of the dynamic power supply current, both quiescent and transient, of the circuit under test. In an off-chip measurement, the global interconnect impedance associated with the chip package and the test equipment and, also, the chip input/output cells will complicate the extraction of the information provided by the current waveform of the circuit under test. Thus, the supply current is measured on-chip by a built-in current sensor integrated in the die itself. To avoid the effective reduction of the voltage supply, the measurement is performed in parallel by replicating the current that flows through selected branches of the analog circuit. With the aim of reducing the test equipment requirements, the built-in current sensor output generates digital level pulses whose width is related to the amplitude and duration of the circuit current transients. In this way the defective circuit is exposed by comparing the digital signature of the circuit under test with the expected one for the fault-free circuit. A fault evaluation has been carried out to check the efficiency of the proposed test method. It uses a fault model that considers catastrophic and parametric faults at transistor level. Two benchmark circuits have been fabricated to experimentally verify the defect detection by the built-in current sensor. One is an operational amplifier; the other is a structure of switched current cells that belongs to an analog-to-digital converter.     

A 1.0-mW, 71-dB SNDR,fourth-order ΣΔ interface circuit for MEMS microphones

In this paper an integrated interface circuit for condenser MEMS microphones is presented. It consists of an input buffer followed by a multi-bit (12-levels), analog, second-order ΣΔ modulator and a fully-digital, single-bit, fourth-order ΣΔ modulator, thus providing a single-bit output signal with fourth order noise shaping, compatible with standard audio chipsets. The circuit, supplied with 3.3 V, exhibits a current consumption of 215 μA for the analog part and 95 μA for the digital part. The measured signal-to-noise and distortion ratio (SNDR) is 71 dB, with an input signal amplitude as large as −1.8 dB with respect to full-scale, obtained thanks to the use of a feed-forward architecture in the analog ΣΔ modulator, which relaxes the voltage swing requirements of the operational amplifiers. The test chip, fabricated in a 0.35-μm CMOS process, occupies an area of 3 mm², including pads.     

一种适应高多普勒频偏的突发传输高效导频图案

导频符号辅助调制技术广泛应用于数字通信系统的突发传输。在频偏范围较大和信噪比较低时,现有的前后式导频方案的频偏估计误差会远高于理论下界。该文研究了频偏估计最大似然检测量的主瓣和旁瓣分布,分析了对称分布导频图案在频偏估计时的模糊问题。在此基础上提出了一种新的混合对称式导频图案,并给出了相应的参数选取原则。新导频图案能够在较低的信噪比下具有大的频偏估计范围和较高的估计精度。仿真结果验证了新导频图案的良好性能。     

Concurrent Zero Knowledge, Revisited

We provide a more general and, in our eyes, simpler variant of Prabhakaran, Rosen and Sahai’s (FOCS ’02, pp. 366–375, 2002) analysis of the concurrent zero-knowledge simulation technique of Kilian and Petrank (STOC ’01, pp. 560–569, 2001).     

A Microstrip Fed Patch Antenna with Two Parasitic Invert L Stubs for Dual-Band WLAN Applications

A novel microstrip fed dual-band design patch antenna with two parasitic invert L stubs for 2.4/5- GHz wireless applications is presented in this paper. Printed on a dielectric substrate of FR4 with relative permittivity of 4.4 and thickness of 1 mm, and fed by a 50Ω microstrip line, the patch antenna with two parasitic invert L stubs is demonstrated to generate three resonant modes to cover 2.4/5.2/5.8- GHz wireless local area network (WLAN) bands with satisfactory radiation characteristics. Experimental and simulated S parameters are presented. Parameters sweep and simulated radiation patterns are demonstrated.     

Scenario based techno-business analysis of service platforms and their service portfolios

This work focuses on techno-business analysis of service platforms and service portfolios. Service platform (SP) hosts services and enabling service functionality. Service providers deliver two main products: end-user services to their customers and enablers to other business actors. 3rd party service providers combine enablers with their own functionality, wrap them in end-user services and deliver them to their customers.