A Golden Section approach to optimization of automotive friction materials

A Golden Section approach combined with relational grade analysis is proposed as an experimental design tool helpful in the development of new automotive friction materials. Golden Section was used to design the volume fraction of the components systematically. The changes in friction performance (friction coefficient and wear) measured using Friction Assessment and Screening Test (FAST) can be correlated with component variations by use of relational grade analysis. This approach was utilized to optimize a non-metallic friction material containing seven ingredients including two fibers (aramid and slag fiber), four fillers (Al₂O₃, BaSO₄, graphite and nitrile rubber) and one binder (benzoxazine). The volume fraction of seven components was varied simultaneously in order to optimize the parameters of friction coefficient and wear with a minimum number of tests. Three phases were performed to find the optimal proportion of the components. The optimized friction performance was obtained after doing 19 formulation experiments.     

A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme

This paper describes a 32-KB two-read, one-write ported L0 cache for 4.5-GHz operation in 1.2-V 130-nm dual-V/sub TH/ CMOS technology. The local bitline uses a leakage-tolerant self reverse-bias (SRB) scheme with nMOS source-follower pullup access transistors, while preserving robust full-swing operation. Gate-source underdrive of -220 mV on the bitline read-select transistors is established without external bias voltages or gate-oxide overstress. Device-level measurements in the 130-nm technology show 72/spl times/ bitline active leakage reduction, enabling low-V/sub TH/ usage, 40% bitline keeper downsizing, and 16 bitcells/bitline. 11% faster read delay and 2/spl times/ higher dc noise robustness are achieved compared with high-performance dual-V/sub TH/ bitline scheme. Sustained performance and robustness benefits of the SRB technique against conventional dynamic bitline with scaling to 100- and 70-nm technology is also presented.     

TD-SCDMA技术及市场分析

TD-SCDMA技术优势 2000年5月,在土耳其伊斯坦布尔召开的国际电联大会上,TD-SCDMA被国际电联接纳为第三代移动通信系统标准之一,这标志着中国在移动通信技术领域已经进入世界先进行列.     

Closed-loop optimal control-enabled piezoelectric microforce sensors

This paper presents a closed-loop optimally controlled force-sensing technology with applications in both micromanipulation and microassembly. The microforce-sensing technology in this paper is based on a cantilevered composite beam structure with embedded piezoelectric polyvinylidene fluoride (PVDF) actuating and sensing layers. In this type of sensor, the application of an external load causes deformation within the PVDF sensing layer. This generates a signal that is fed through a linear quadratic regulator (LQR) optimal servoed controller to the PVDF actuating layer. This in turn generates a balancing force to counteract the externally applied load. As a result, a closed feedback loop is formed, which causes the tip of this highly sensitive sensor to remain in its equilibrium position, even in the presence of dynamically applied external loads. The sensor's stiffness is virtually improved as a result of the equilibrium position whenever the control loop is active, thereby enabling accurate motion control of the sensor tip for fine micromanipulation and microassembly. Furthermore, the applied force can be determined in real time through measurement of the balance force.     

雷达仿真系统中电磁干扰环境的仿真设计和实施

雷达仿真系统是为检测雷达设备的抗干扰能力以及在各种电磁环境下的工作性能而设计的，包括有源干扰和无源干扰的模拟仿真。本文阐述了无源干扰即杂波的散射模型和仿真过程；从同步脉冲干扰的基本原理出发，阐明在雷达工作环境仿真系统中距离拖引、速度拖引、虚假目标等同步脉冲有源干扰的设计和实施过程；并针对工作在搜索和跟踪交替模式下的相控阵雷达提出自适应综合干扰方式；最后分析并总结了系统仿真时为真实、有效地模拟电磁干扰环境应注意的关键问题。     

Hydrogenated amorphous silicon thin-film transistor arrays fabricated by digital lithography

A jet-printed digital-lithographic method, in place of conventional photolithography, was used to fabricate 64 /spl times/ 64 pixel (300 /spl mu/m pitch) matrix addressing thin-film transistor (TFT) arrays. The average hydrogenated amorphous silicon TFT device within an array had a threshold voltage of /spl sim/3.5 V, carrier mobility of 0.7 cm/sup 2//V/spl middot/s, subthreshold slope of 0.76 V/decade, and an on/off ratio of 10/sup 8/.     

A NEW LARGE CAVITATION CHANNEL IN CHINA SHIP SCIENTIFIC RESEARCH CENTER

1 .　INTRODUCTIONIntherecentdecades ,itisrealizedthatitisquitenecessarytocarryouttestsathighReynoldsnumberwithalowbackgroundnoiselevelinordertomeetmoreandmoreurgentneedsofmodernnavyandmaritimeindustry .Anewlargecavita tionchannelisdevelopedinCSSRCfortestingcompletehull/ propulsor/appendagesarrange ments[1] .Itrepresentsoneofthelatestintechno logicallyadvancedlargecavitationtestfacilities.Inthefollowingsections ,thefeaturesandthefirsttestresultsofthechannelwillbedescribed .2 .　DICRIP…     

双层堤基的井涌破坏与无害管涌

双层堤基水文地质结构特殊，堤基承压水常具独特的“渗而不流”特征。在“不流”条件下，堤后盖层薄弱处受超高承压水头顶裂破坏，产生的局部冒水孔实属承压自流井，由此形成的管涌实质为井涌。底部进水的承压井流影响范围不大，井涌的破坏范围更小，据此可区分出有害管涌与无害管涌。前者局限于堤脚附近，小范围压渗为首选方案；对后者，既无需专门防治，更不必追求根治。