A high-yield fabrication process for silicon neural probes

There is a great need for silicon microelectrodes that can simultaneously monitor the activity of many neurons in the brain. However, one of the existing processes for fabricating silicon microelectrodes-reactive-ion etching in combination with anisotropic KOH etching-breaks down at the wet-etching step for device release. Here we describe a modified wet-etching sidewall-protection technique for the high-yield fabrication of well-defined silicon probe structures, using a Teflon shield and low-pressure chemical vapor deposition (LPCVD) silicon nitride. In the proposed method, a micro-tab holds each individual probe to the central scaffold, allowing uniform anisotropic KOH etching. Using this approach, we obtained a well-defined probe structure without device loss during the wet-etching process. This simple method yielded more accurate fabrication and an improved mechanical profile.     

Designing Thin,Ultrastretchable Electronics with Stacked Circuits and Elastomeric Encapsulation Materials

Many recently developed soft, skin‐like electronics with high performance circuits and low modulus encapsulation materials can accommodate large bending, stretching, and twisting deformations. Their compliant mechanics also allows for intimate, nonintrusive integration to the curvilinear surfaces of soft biological tissues. By introducing a stacked circuit construct, the functional density of these systems can be greatly improved, yet their desirable mechanics may be compromised due to the increased overall thickness. To address this issue, the results presented here establish design guidelines for optimizing the deformable properties of stretchable electronics with stacked circuit layers. The effects of three contributing factors (i.e., the silicone interlayer, the composite encapsulation, and the deformable interconnects) on the stretchability of a multilayer system are explored in detail via combined experimental observation, finite element modeling, and theoretical analysis. Finally, an electronic module with optimized design is demonstrated. This highly deformable system can be repetitively folded, twisted, or stretched without observable influences to its electrical functionality. The ultrasoft, thin nature of the module makes it suitable for conformal biointegration.     

Room‐Temperature Metallic Fusion‐Induced Layer‐by‐Layer Assembly for Highly Flexible Electrode Applications

To fabricate flexible electrodes, conventional silver (Ag) nanomaterials have been deposited onto flexible substrates, but the formed electrodes display limited electrical conductivity due to residual bulky organic ligands, and thus postsintering processes are required to improve the electrical conductivity. Herein, an entirely different approach is introduced to produce highly flexible electrodes with bulk metal–like electrical conductivity: the room‐temperature metallic fusion of multilayered silver nanoparticles (NPs). Synthesized tetraoctylammonium thiosulfate (TOAS)‐stabilized Ag NPs are deposited onto flexible substrates by layer‐by‐layer assembly involving a perfect ligand‐exchange reaction between bulky TOAS ligands and small tris(2‐aminoethyl)amine linkers. The introduced small linkers substantially reduce the separation distance between neighboring Ag NPs. This shortened interparticle distance, combined with the low cohesive energy of Ag NPs, strongly induces metallic fusion between the close‐packed Ag NPs at room temperature without additional treatments, resulting in a high electrical conductivity of ≈1.60 × 10⁵ S cm^?1 (bulk Ag: ≈6.30 × 10⁵ S cm^?1). Furthermore, depositing the TOAS–Ag NPs onto cellulose papers through this approach can convert the insulating substrates into highly flexible and conductive papers that can be used as 3D current collectors for energy‐storage devices.     

H2 plasma treatment at the p/i interface of a hydrogenated amorphous Si absorption layer for high‐performance Si thin film solar cells

Plasma treatment (PT) of the buffer layer for highly H₂‐diluted hydrogenated amorphous silicon (a‐Si:H) absorption layers is proposed as a technique to improve efficiency and mitigate light‐induced degradation (LID) in a‐Si:H thin film solar modules. The method was verified for a‐Si:H single‐junction and a‐Si:H/microcrystalline silicon (µc‐Si:H) tandem modules with a size of 200 × 200 mm² (aperture area of 382.5 cm²) under long‐term light exposure. H₂ PT at the p/i interface was found to eliminate non‐radiative recombination centers in the buffer layer, and plasma‐enhanced chemical vapor deposition at low radio‐frequency power was found to suppress the generation of defects during the growth of a‐Si:H absorption layers on the treated buffer layers. With optimized H₂ PT of the a‐Si:H single‐junction module, the stabilized short circuit current and fill factor increased, and the stabilized open circuit voltage moves beyond its initial value. The results demonstrate 7.7% stabilized efficiency and 10.5% LID for the a‐Si:H single‐junction module and 10.82% stabilized efficiency and 7.76% LID for the a‐Si:H/µc‐Si:H tandem module. Thus, the growth of an a‐Si:H absorption layer on a H₂ PT buffer layer can be considered as a practical method for producing high‐performance Si thin film modules. Copyright © 2012 John Wiley & Sons, Ltd.     

Topology design and bridge-capacity assignment for interconnecting token ring LANs: A simulated annealing approach

We address the problem of determining the topology and bridge-capacity assignments for a network connecting a number of token rings via source-routing bridges. The objective is to minimize the cost of bridge installations while meeting the network users' performance requirements. The problem is modeled as a mixed 0–1 integer program. A comparison is given between two solution algorithms: a simulated annealing algorithm using the flow-deviation algorithm for each routing subproblem, and a drop algorithm using the simplex method for the same subproblems to provide benchmark solutions. In the former algorithm, the routing subproblem is formulated as a nonlinear program with penalty functions to model node and link capacity constraints, and in the latter as a multicommodity flow model with the same capacity constraints. Computational results show that the simulated-annealing/flow-deviation algorithm produced substantially better solutions than the LP-based drop algorithm.     

舰船尾流激光制导方法的研究

为了研究鱼雷的激光尾流制导方法,分析了舰船航行时所产生尾流的几何特征和光学性质,讨论了舰船尾流中不易在短时间内消失的微气泡对激光的散射特性,提出了利用激光在尾流区域内、外传输时,其前向或后向散射激光在时域、频域和空域中光学参数的变化来快速、准确地判别鱼雷是否进入、穿出尾流,从而导引鱼雷沿目标舰船的航迹靠近目标的新型鱼雷制导方法。讨论了实现鱼雷激光尾流制导的几种不同途径,得出了上视激光尾流制导是一种既不会破坏鱼雷雷体的流线性结构,又可以通过激光扫描来确定尾流边界的先进的鱼雷制导方法的结论。     

Implementation of an SDR platform using GPU and its application to a 2?��?2 MIMO WiMAX system

Conventional communication systems have been implemented using digital signal processors (DSPs) and/or field programmable gate arrays (FPGAs), especially for software defined radio (SDR) functionality. We propose a scheme that uses a graphics processing unit (GPU) in place of the conventional DSPs or FPGAs for the implementation of an SDR-based communication system. The GPU, a high-speed parallel processor with multiple arithmetic logic units, is adopted for the signal processing of the physical layer required for the parallel processing in an SDR system. The compute unified device architecture (CUDA) based on the C language provides a software development kit (SDK) for the modem application of the GPU. Therefore we utilize the CUDA SDK to implement the real-time modem function. This paper presents an implementation of a 2 × 2 multiple-input multiple-output (MIMO) WiMAX system employing a GPU as the real-time modem. By installing a radio frequency module on top of the GPU modem, we implement a real-time transmission system for video data. The performance of the proposed GPU-based system is demonstrated by comparing its operation time against that of the conventional DSP-based system.     

Evaluation of acid and enzyme hydrolytic methods for the determination of edible aroid starch content

The starch content of four edible aroid (Araceae) cultivars was determined using acid and enzyme methods of hydrolysis. Hydrolysates were analysed using ferricyanide reduction, glucose oxidase and high performance liquid chromatography methods. Differences in starch values were obtained between the method of sugar analysis used when acid hydrolysis of samples was employed. The results obtained using enzyme hydrolysis, however, showed no significant differences between the methods of sugar analysis used. The results of these experiments indicate that, to obtain accurate starch values for edible aroids using the least expensive options, it is recommended that acid hydrolysis and the glucose oxidase-peroxidase glucose-specific assay methods or enzyme hydrolysis and ferricyanide sugar analysis be used. Starch degradation of ungelatinised samples by enzymic hydrolysis was very limited and showed considerable cultivar variation.     

Analysis and prevention of DRAM latch-up during power-on

The occasional power-on latch-up phenomenon of DRAM modules with a data bus shared by multiple DRAM chips on different modules was investigated and the circuit techniques for latch-up prevention were presented. Through HSPICE simulations and measurements, the latch-up triggering source was identified-to be the excessive voltage drop at the n-well pick-up of the CMOS transmission gate of read data latch circuit due to the short-circuit current which flows when the bus contention occurs during power-on. By extracting the HSPICE Gummel-Poon model parameters of the parasitic bipolar transistors of DRAM chips from the measured I-V and C-V data, HSPICE simulations were performed for the power-on latch-up phenomenon of DRAM chips. Good agreements were achieved between measured and simulated voltage waveforms. In order to prevent the power-on latch-up even when the control signals (RAS, GAS) do not track with the power supply, two circuit techniques were presented to solve the problem. One is to replace the CMOS transmission gate by a CMOS tristate inverter in the DRAM chip design and the other is to start the CAS-BEPORE-RAS (CBR) refresh cycle during power-on and thus disable all the Dout buffers of DRAM chips during the initial power-on period     

Low‐Power Nonvolatile Charge Storage Memory Based on MoS2 and an Ultrathin Polymer Tunneling Dielectric

Low‐power, nonvolatile memory is an essential electronic component to store and process the unprecedented data flood arising from the oncoming Internet of Things era. Molybdenum disulfide (MoS₂) is a 2D material that is increasingly regarded as a promising semiconductor material in electronic device applications because of its unique physical characteristics. However, dielectric formation of an ultrathin low‐k tunneling on the dangling bond‐free surface of MoS₂ is a challenging task. Here, MoS₂‐based low‐power nonvolatile charge storage memory devices are reported with a poly(1,3,5‐trimethyl‐1,3,5‐trivinyl cyclotrisiloxane) (pV3D3) tunneling dielectric layer formed via a solvent‐free initiated chemical vapor deposition (iCVD) process. The surface‐growing polymerization and low‐temperature nature of the iCVD process enable the conformal growing of low‐k (≈2.2) pV3D3 insulating films on MoS₂. The fabricated memory devices exhibit a tunable memory window with high on/off ratio (≈10⁶), excellent retention times of 10⁵ s with an extrapolated time of possibly years, and an excellent cycling endurance of more than 10³ cycles, which are much higher than those reported previously for MoS₂‐based memory devices. By leveraging the inherent flexibility of both MoS₂ and polymer dielectric films, this research presents an important milestone in the development of low‐power flexible nonvolatile memory devices.