Fully Integrated CMOS Power Amplifier With Efficiency Enhancement at Power Back-Off

This paper presents a new approach for power amplifier design using deep submicron CMOS technologies. A transformer based voltage combiner is proposed to combine power generated from several low-voltage CMOS amplifiers. Unlike other voltage combining transformers, the architecture presented in this paper provides greater flexibility to access and control the individual amplifiers in a voltage combined amplifier. In this work, this voltage combining transformer has been utilized to control output power and improve average efficiency at power back-off. This technique does not degrade instantaneous efficiency at peak power and maintains voltage gain with power back-off. A 1.2 V, 2.4 GHz fully integrated CMOS power amplifier prototype was implemented with thin-oxide transistors in a 0.13 mum RF-CMOS process to demonstrate the concept. Neither off-chip components nor bondwires are used for output matching. The power amplifier transmits 24 dBm power with 25% drain efficiency at 1 dB compression point. When driven into saturation, it transmits 27 dBm peak power with 32% drain efficiency. At power back-off, efficiency is greatly improved in the prototype which employs average efficiency enhancement circuitry.     

视觉信号质量评价的挑战与新进展

While quality assessment is essential for testing, optimizing, benchmarking, monitoring, and inspecting related systems and services, it also plays an essential role in the design of virtually all visual signal processing and communication algorithms, as well as various related decision-making processes. In this pa-per, we first provide an overview of recently derived quality assessment approaches for traditional visual signals (i.e., 2D im-ages/videos), with highlights for new trends (such as machine learning approaches). On the other hand, with the ongoing development of devices and multimedia services, newly emerged visual signals (e.g., mobile/3D videos) are becoming more and more popular. This work focuses on recent progresses of quality metrics, which have been reviewed for the newly emerged forms of visual signals, which include scalable and mobile videos, High Dynamic Range (HDR) images, image segmentation results, 3D images/videos, and retargeted images.     

Simulating process-induced gate oxide damage in circuits

Advanced processing techniques such as plasma etching and ion implantation can damage the gate oxides of MOS devices and thus pose a problem to circuit reliability. In this paper, we present a simulator which predicts oxide failure rates during and after processing and pinpoints strong charging current locations in the layout where changes can be made to improve circuit hot-carrier reliability. We present the models and experimental results used to develop the simulator and demonstrate the usefulness of this simulator     

Response to remarks by J.R. Wait on the comments and reply to“The electromagnetic field of a vertical electric dipole over theEarth or sea”

In his remarks on the comments by Yokoyama (see ibid., vol.43, no.5, p.541-42, 1995) and the reply by King and Sandler (see ibid., vol.43, no.5, p.542-44, 1995) regarding our paper (see ibid., vol.42, no.3, p.382-9, 1994) J. R. Wait (see ibid., vol.44, no.2, p.271-72, 1996) makes a number of statements that require correction. These are considered in turn, but since they all center about the definition of the Sommerfeld numerical distance, this is introduced first. In a paper by Norton (1937), which is later quoted and applied by Wait, a formula is given for the generalized numerical distance for the height z and radial distance ρ due to a vertical dipole at the height d in the air (region 2, real wave number k_z) over a conducting or dielectric region 1 (complex wave number k₁). It is important to emphasize that the purpose of this response is not to belittle the important pioneer work of Norton, Wait, and others. Interest a half century ago was in communication over the surface of the Earth and sea with (z+d)²≪ρ². In this range, their formulas are accurate. However, recent progress which eliminates the restriction (z+d)²≪ρ² or k₂ρ≫1 should not be ignored by blindly using restricted formulas where they do not apply     

Solar cell efficiency tables (version 29)

Consolidated tables showing an extensive listing of the highest independently confirmed efficiencies for solar cells and modules are presented. Guidelines for inclusion of results into these tables are outlined and new entries since June 2006 are reviewed. Copyright © 2006 John Wiley & Sons, Ltd.     

Very high-order microring resonator filters for WDM applications

High-order microring resonators having from 1 to 11 coupled cavities are demonstrated. These filters exhibit low loss, flat tops, and out-of-band rejection ratios that can exceed 80 dB. They achieve performance that is suitable for commercial applications.     

Fields and currents in the organs of the human body when exposed topower lines and VLF transmitters

A study is made of the electric fields and currents induced in the organs of the human body when exposed to high-voltage 50-60-Hz transmission lines and 10-30-kHz high-power transmitters. Relevant analyses previously carried out are summarized and supplemented with detailed investigations that complete the picture. Incomplete, misleading, and incorrect statements and methods in the related literature are pointed out, completed, and corrected. The major contribution is to provide quantitatively accurate, relatively simple analytic formulas that relate the incident electric field to the induced field in the organs of the body. The formulation and solution of the underlying integral equation are carried out in an Appendix     

Embedded TFT nand-Type Nonvolatile Memory in Panel

A new NAND-type nonvolatile memory with a field-enhancing tip structure embedded in low-temperature polycrystalline silicon (LTPS) panel was demonstrated on a glass substrate for the first time. A thin-film transistor (TFT) metal-oxide-nitride-oxide-silicon (MONOS) device based on sequential lateral solidification crystallization with a fully depleted poly-Si channel, an oxide-nitride-oxide stack gate dielectric, and a metal gate is integrated into a NAND array. A NAND test array based on p-channel LTPS TFTs exhibits good cycling endurance and data retention properties and negligible program and read disturbance. These results strongly support the claim that this TFT-MONOS device is a promising candidate for use in embedded nonvolatile memory for system-on-panel and 3-D IC applications