Effect of hydrogen annealing on hot-carrier instability of X-Ray irradiated CMOS devices

In the very large scale integration (VLSI) technology, the need for high density and high performance integrated circuit (IC) chip demands advanced processing techniques that often result in the generation of high energy particles and photons. Frequently, the radiation damage are introduced by these energetic particles and photons during device processing. The radiation damage created by x-ray irradiation, which can often occur during metal sputtering process, has been shown to potentially enhance hot-carrier instability if the neutral traps which act as electron or hole traps in the silicon dioxide is not annealed out. In this paper, we investigate the effects of annealing using different hydrogen contents and temperatures on the device characteristics and hot carrier instability of 0.5 μm CMOS devices after 1500 mJ/cm² synchrotron x-ray irradiation. Three different annealing conditions were employed; 400° C H₂, 450° C H₂, and 400° C H₂ + N₂. It is found that for all three different hydrogen anneals the normal characteristics of irradiated CMOS devices can be effectively recovered. The hot-carrier instability of bothp- andn-channel MOSFETs are significantly enhanced after x-ray irradiation due to the creation of neutral traps and positively charged oxide traps. After high H₂ (100%) concentration anneals at 450° C, the hot-carrier instability in irradiatedn-channel devices is greatly reduced and comparable to the non-irradiated devices. Although the hot-carrier instability inp-channel devices is also significantly reduced after annealing, the threshold voltage shifts are still enhanced as compared to the devices without exposure to x-ray irradiation during maximum gate current stress. For those non-irradiated, but hydrogen-annealedp-channel devices, the hot-carrier instability was observed to be worse than the non-irradiated device without hydrogen annealing.     

Two schemes for detecting CMOS analog faults

A design-for-testability scheme for detecting CMOS analog faults was reported by Favalli et al. (see ibid., vol.25, no.5, p.1239-46, 1990). The authors propose two alternative designs, one for small circuits and another for large circuits, which require significantly less area overhead (about 1/4 to 1/3) than that of Favalli's design. With the proposed modification in the first design, the untestable problem, which occurred in Favalli's design, can be alleviated. Furthermore, the proposed schemes are also fit to be implemented in VLSI circuits     

Nanoporous platinum counter electrodes by glancing angle deposition for dye-sensitized solar cells

We report an effective way to produce nanoporous Pt counter electrodes of dye-sensitized solar cells by the glancing-angle deposition (GLAD) technique. By controlling the orientation of the substrate relative to the incident Pt vapor flux during the deposition, nanoporous films composed of inclined nm-scale columns were produced through the self-shadowing effect. Pt counter electrodes having varied nanoporous structures were characterized for their morphological and electrochemical properties, and were subjected to device studies to establish the correlation with DSSC characteristics/performances. The results suggest that the nanoporous GLAD Pt electrodes can effectively enhance active surface areas, the catalytic ability and charge exchange at the Pt/electrolyte interface of a DSSC. As a result, the quantum efficiency, short-circuit current, and power conversion efficiency of the DSSC can be enhanced by up to 12–13% with using the nanoporous GLAD Pt counter electrodes.     

Weak inversion charge injection in analog MOS switches

The on-chip test circuit for examining the charge injection in analog MOS switches has been described in detail, and has been fabricated and characterized. Mixed-mode circuit and device simulations have been performed, creating excellent agreements not only with the experimental waveforms but also with the measured switch-induced error voltage. Further investigation of the experimental and simulated results has separated the charge injection into three distinct components: i) the channel charges in strong inversion; ii) the channel charges in weak inversion; and iii) the charges coupled through the gate-to-diffusion overlap capacitance. Important observations concerning the weak inversion charge injection have been drawn from the waveform of the current through the switched capacitor. In this work the channel charges in weak inversion have exhibited a 20% contribution to the switch-induced error voltage on a switched capacitor     

Cost-Effective Joint Echo-NEXT Canceller Designs for 10GBase-T Ethernet Systems Based on a Shortened Impulse Response Filter (SIRF) Scheme

Echo canceller plays an important role in the full-duplex communication system. Conventional implementations of echo cancellers are often the adaptive transversal filter architectures due to the simplicity and robustness of stability and convergence. However, the conventional echo cancellers suffer from high cost problem especially when the response time of the echo is long. In this paper, a new cost-efficient architecture of echo cancellers, targeting on 10GBase-T Ethernet System, is presented. The proposed scheme inherits the concept of channel shortening which is widely employed in DSL systems. A shortened impulse response filter is implemented at the receiver to shorten the impulse response of the echo signal. Hence, the overall cost of echo cancellers can be reduced. We generalize the channel shortening architecture to a joint multi-channel shortening scheme. The joint multi-channel shortening architecture can be applied to multiple-input multiple-output wireline communication systems to further reduce both the cost of echo and near-end crosstalk (NEXT) cancellers. We apply the proposed scheme to 10GBase-T Ethernet system. The simulation results show that the proposed echo and NEXT cancellers can save up to 35% hardware cost compared to the conventional transversal implementations.

40-Gb/s Time-Division-Multiplexed Passive Optical Networks Using Downstream OOK and Upstream OFDM Modulations

In this investigation, we first propose and investigate a 40-Gb/s time-division-multiplexed passive optical network (TDM-PON) using four wavelength-multiplexed signals in both downstream and upstream traffic. Here, each downstream signal uses 10-Gb/s on–off keying (OOK) format encoded by a Mach–Zehnder modulator (MZM) in 1.5-$mu{hbox {m}}$ band. And each upstream channel utilizes the highly spectral efficient 10-Gb/s orthogonal frequency-division-multiplexing quadrature amplitude modulation (OFDM-QAM) generated by directly modulating a 1.3-$mu{hbox {m}}$ laser. Based on the proposed scheme, 40-Gb/s data traffic in a TDM-PON can be obtained easily by using four wavelength-multiplexed channels. In addition, the performance of the proposed PON architecture has also been discussed.      

Nitride-based flip-chip ITO LEDs

Nitride-based flip-chip indium-tin-oxide (ITO) light-emitting diodes (LEDs) were successfully fabricated. It was found that the forward voltage and the 20 mA output power of the flip-chip ITO LED were 3.32 V and 14.5 mW, respectively. Although the operation voltage of such a flip-chip ITO LED was slightly larger, it was found that its output power was much larger than those of conventional nonflip-chip LEDs. It was also found that flip-chip ITO LEDs were more reliable.     

Efficiency improvement of near-ultraviolet InGaN LEDs using patterned sapphire substrates

The use of conventional and patterned sapphire substrates (PSSs) to fabricate InGaN-based near-ultraviolet (410 nm) light-emitting diodes (LEDs) was demonstrated. The PSS was prepared using a periodic hole pattern (diameter: 3 /spl mu/m; spacing: 3 /spl mu/m) on the (0001) sapphire with different etching depths. From transmission-electron-microscopy and etch-pit-density studies, the PSS with an optimum pattern depth (D/sub h/=1.5 /spl mu/m) was confirmed to be an efficient way to reduce the thread dislocations in the GaN microstructure. It was found that the output power increased from 8.6 to 10.4 mW, corresponding to about 29% increases in the external quantum efficiency. However, the internal quantum efficiency (@ 20 mA) was about 36% and 38% for the conventional and PSS LEDs, respectively. The achieved improvement of the output power is not only due to the improvement of the internal quantum efficiency upon decreasing the dislocation density, but also due to the enhancement of the extraction efficiency using the PSS. Finally, better long-time reliability of the PSS LED performance was observed.     

Topology-aided cross-layer fast handoff designs for IEEE 802.11/mobile IP environments

This study first reviews state-of-the-art fast handoff techniques for IEEE 802.11 or Mobile IP networks. Based on that review, topology-aided cross-layer fast handoff designs are proposed for Mobile IP over IEEE 802.1.1 networks. Time-sensitive applications, such as voice over IP (VoIP), cannot tolerate the long layer-2 plus layer-3 handoff delays that arise in IEEE 802.11/Mobile IP environments. Cross-layer designs are increasingly adopted to shorten the handoff latency time. Handoff-related layer-2 triggers may reduce the delay between layer-2 handoff completion and the associated layer-3 handoff activation. Cross-layer topology information, such as the association between 802.11 access points and Mobile IP mobility agents, together with layer-2 triggers, can be utilized by a mobile node to start layer-3 handoff-related activities, such as agent discovery, address configuration, and registration, in parallel with or prior to those of layer-2 handoff. Experimental results indicate that the whole handoff. delay can meet the delay requirement of VoIP applications when layer-3 handoff activities occur prior to layer-2 handoffs.     

平台化ASIC迅速打开市场

平台化专用集成电路(Platform ASIC)是一类新推出的产品,其应用目标是减少上市时间和降低设计成本.从日渐增多的相应新设计可以看出,平台化ASIC前景一片光明.