用于先进PCB制造工艺的叠层封装

在20世纪90年代,球栅阵列封装(BGA)和芯片尺寸封装(CSP)在封装材料和加工工艺方面达到了极限。这2种技术如同20世纪80年代的表面安装器件(SMD)和70年代通孔安装器件(THD)一样,在电学、机械、热性能、尺寸、质量和可靠性方面达到最大值。目前,三维封装正在成为用于未来采用的先进印制板(PCB)制造工艺的下一个阶段。它们可以分为圆片级封装、芯片级封装、和封装面。叠层封装(PoP)是一种封装面叠层封装类型的三维封装技术[15]。     

A simple simultaneous geometric and intensity correction method for echo-planar imaging by EPI-based phase modulation

A technique, based on Echo planar imaging (EPI)-based phase modulation factor maps, is described for correction of EPI distortions resulting from field inhomogeneity. In this paper, a phase modulation factor was employed to remove the distortions. The phase modulation factor was obtained experimentally by collecting EPI images with a spin-echo (TE) spacing, deltaTE, equal to the inter-echo time interval, T(i). Then, the distortions resulting from the field inhomogeneity were removed by modulating the kappa-space data with the phase modulation factor. One of the advantages of this method is that it requires only a few extra scans to collect the information on field inhomogeneity. The proposed method does not require a phase unwrapping procedure for field inhomogeneity correction and, hence, is easier to implement, compared to other techniques. In addition, it corrects geometric distortion as well as intensity distortions simultaneously, which is robust to external noise or estimation error in severely distorted images. In this work, we also compared the proposed technique with others including, a) interpolation method with EPI-based displacement maps, and b) modulation method with phase modulation factor maps generated from spin-echo images. The results suggest the proposed technique is superior in correcting severely distorted images.     

Over GHz electrical circuit model of a high-density multiple line grid array (MLGA) interposer

The multiple line grid array (MLGA) interposer was recently introduced as a future high-density high-speed bonding method. In this paper, we introduce an electrical model and high-frequency characteristics of the MLGA interposer. The high-frequency electrical model was extracted from microwave S-parameter measurements up to 20 GHz as well as from fundamental microwave network analysis. For the parameter fitting process during model extraction, an optimization method was used. Several different types of MLGA interposers were designed, assembled and tested. The test vehicles contained coplanar waveguides, probing pads and an MLGA interposer structure. The height of the MLGA, the conductor shape inside the MLGA, and the dielectric insulator of the MLGA were varied. From the model, an MLGA with a height of 0.4 mm and a polymer dielectric insulator was found to have 203 pH of self inductance, 49 pH of mutual inductance with the nearest ground conductor line, and 186 fF of mutual capacitance. By reducing the height of the MLGA and by using an insulator with a lower dielectric constant, parasitic inductance and capacitance is further reduced. TDR/TDT simulation and measurement showed the validity of the extracted model parameters of the MLGA interposer. Circuit simulation based on the extracted model revealed that the MLGA interposer could be successfully used for microwave device packages up to 20 GHz and for high-speed digital device packages with a clock cycle up to 5 GHz.     

ε‐Branched Flexible Side Chain Substituted Diketopyrrolopyrrole‐Containing Polymers Designed for High Hole and Electron Mobilities

Based on the integrated consideration and engineering of both conjugated backbones and flexible side chains, solution‐processable polymeric semiconductors consisting of a diketopyrrolopyrrole (DPP) backbone and a finely modulated branching side chain (ε‐branched chain) are reported. The subtle change in the branching point from the backbone alters the π?π stacking and the lamellar distances between polymer backbones, which has a significant influence on the charge‐transport properties and in turn the performances of field‐effect transistors (FETs). In addition to their excellent electron mobilities (up to 2.25 cm² V^?1 s^?1), ultra‐high hole mobilities (up to 12.25 cm² V^?1 s^?1) with an on/off ratio (I_on/I_off) of at least 10⁶ are achieved in the FETs fabricated using the polymers. The developed polymers exhibit extraordinarily high electrical performance with both hole and electron mobilities superior to that of unipolar amorphous silicon.     

Metal Organic Framework-MXene Nanoarchitecture for Fast Responsive and Ultra-Stable Electro-Ionic Artificial Muscles

Electro-ionic soft actuators, capable of continuous deformations replacing non-compliant rigid mechanical components, attract increasing interest in the field of next-generation metaverse interfaces and soft robotics. Here, a novel MXene (Ti₃C₂T_x) electrode anchoring manganese-based 1,3,5-benzenetricarboxylate metal-organic framework (MnBTC) for ultrastable electro-ionic artificial muscles is reported. By a facile supramolecular self-assembly, the Ti₃C₂T_x-MnBTC hybrid nanoarchitecture forms coordinate bond, hydrogen bond, and hydrophilic interaction with the conducting polymer of poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS), resulting in a mechanically flexible and electro-ionically active electrode. The superior electrical and electrochemical performances of the electrode stem from the synergistic effects between intrinsically hierarchical nanoarchitecture of MnBTC and rapid electron transport behavior of Mxene, leading to fast diffusion and accommodation of ions in the ion-exchangeable membrane. The developed artificial muscle based on Ti₃C₂T_x-MnBTC is found to exhibit high bending displacement (12.5 mm) and ultrafast response time (0.77 s) under a low driving voltage (0.5 V), along with wide frequency response (0.1–10 Hz) and exceptional stability (98% retention at 43,200 s) without any distortion of actuation performance. Furthermore, the designed electro-active artificial muscle is successfully used to demonstrate mimicry of eye motions including eyelid blinking and eyeball movement in a doll.     

Chemically Recyclable Conjugated Polymer and One-Shot Preparation of Thermally Stable and Efficient Bulk-Heterojunction from Recycled Monomer

Recyclable conjugated polymers are important for realizing eco-friendly electronics with advantages of solution processability and flexibility. A recyclable conjugated polymer, PY-TIP is developed, of which a key monomer is successfully extracted via a mild depolymerization process and is reused for the synthesis of novel conjugated polymers. One-shot preparation of polymer acceptor and its bulk-heterojunction (BHJ) is demonstrated from the recycled monomer, Y5-TA, for the first time and the resulting BHJ film shows optimal nanoscale morphology for efficient charge generation and transport. As a result, the solar cells prepared using the BHJ film show a higher efficiency of 13.08% and much improved thermal and mechanical stability compared with those based on the small molecular acceptor. These results are important in that the various polymers can be prepared from the recycled monomer in a solid state without organic solvents and purification step and this strategy is effective for improving the thermal and mechanical stability of the BHJ film as well as achieving high photovoltaic performance. PY-TIP is exemplary in that it can reproduce its monomer which can be used to synthesize conjugated polymers with novel chemical structures and physical properties. This work provides a design guideline for developing recyclable conjugated polymers with dynamic covalent bonds.     

Organic Semiconductor Cocrystal for Highly Conductive Lithium Host Electrode

In this work, a highly conductive organic cocrystal is investigated as an anode material for conducting agent‐free lithium‐ion battery (LIB) electrodes. A unique morphology of semiconducting fullerene (C₆₀) and contorted hexabenzocoronene (cHBC) is developed as a cocrystal that efficiently enhances the electron transfer during discharge and charge processes due to the formation of a well‐defined junction between C₆₀ and cHBC. In particular, the present study reveals the exact cocrystal phase of orthorhombic Pnnm using grazing incidence X‐ray diffraction characterization and computational methods. The detailed cocrystal structure analysis indicates that the columnar structure of C₆₀/cHBC cocrystal facilitates the reliable vacant sites for Li⁺ storage, which ultimately enhances the reversible capacity to 330 mAh g^–1 at 0.1 A g^–1 with long cyclability of 600 cycles in the absence of a conducting agent. Furthermore, the rate performance of the C₆₀/cHBC cocrystal anode is improved compared to that of the graphite anode, indicating that the cocrystal formation between C₆₀ and cHBC enhances the charge transport at a high current density. It demonstrates that the approach of this study can be a promising strategy for preparing conducting agent‐free organic cocrystal anodes, which also provides a viable design rule for high‐performance LIBs electrodes.     

Implementation of an SDR platform using GPU and its application to a 2?��?2 MIMO WiMAX system

Conventional communication systems have been implemented using digital signal processors (DSPs) and/or field programmable gate arrays (FPGAs), especially for software defined radio (SDR) functionality. We propose a scheme that uses a graphics processing unit (GPU) in place of the conventional DSPs or FPGAs for the implementation of an SDR-based communication system. The GPU, a high-speed parallel processor with multiple arithmetic logic units, is adopted for the signal processing of the physical layer required for the parallel processing in an SDR system. The compute unified device architecture (CUDA) based on the C language provides a software development kit (SDK) for the modem application of the GPU. Therefore we utilize the CUDA SDK to implement the real-time modem function. This paper presents an implementation of a 2 × 2 multiple-input multiple-output (MIMO) WiMAX system employing a GPU as the real-time modem. By installing a radio frequency module on top of the GPU modem, we implement a real-time transmission system for video data. The performance of the proposed GPU-based system is demonstrated by comparing its operation time against that of the conventional DSP-based system.     

Development of the Base Station Controller and Manager in the CDMA Mobile System

The base station (BS) in the CDMA Mobile System (CMS) connects calls through the radio interface and is designed to provide mobile subscribers with high quality service in spite of mobile subscribers’ motions. The BS consists of multiple base station transceiver subsystems (BTSs), a base station controller (BSC) and a base station manager (BSM). This paper is concerned with the BSC and the BSM. The BSC is located between the BTSs and the mobile switching center (MSC) connected with the public network, and is responsible for controlling mobile calls from and to mobile subscribers via the BTSs. The BSM provides operator-interfaces per the BS and takes responsibility of operation and maintenance (OAM) of the BS. Design of the BSC is based on two module types: functional module and unit module. The functional module is used to support new services easily and the unit module to increase the system capacity economically. Both modular types are easily achieved by inserting the corresponding modules to the system. Particularly, in order to efficiently support the soft handover which is one of CDMA superior advantages, the BSC adopts a large high-speed packet switch connecting up to 512 BTSs, and thus mobile subscribers can be provided with soft handover in high probability. The BSM is based on a commercial workstation to support OAM functions efficiently and guarantee high reliability of the functions. The BSM uses graphical user interface (GUI) for efficient OAM functions of the BS.     

Analysis and prevention of DRAM latch-up during power-on

The occasional power-on latch-up phenomenon of DRAM modules with a data bus shared by multiple DRAM chips on different modules was investigated and the circuit techniques for latch-up prevention were presented. Through HSPICE simulations and measurements, the latch-up triggering source was identified-to be the excessive voltage drop at the n-well pick-up of the CMOS transmission gate of read data latch circuit due to the short-circuit current which flows when the bus contention occurs during power-on. By extracting the HSPICE Gummel-Poon model parameters of the parasitic bipolar transistors of DRAM chips from the measured I-V and C-V data, HSPICE simulations were performed for the power-on latch-up phenomenon of DRAM chips. Good agreements were achieved between measured and simulated voltage waveforms. In order to prevent the power-on latch-up even when the control signals (RAS, GAS) do not track with the power supply, two circuit techniques were presented to solve the problem. One is to replace the CMOS transmission gate by a CMOS tristate inverter in the DRAM chip design and the other is to start the CAS-BEPORE-RAS (CBR) refresh cycle during power-on and thus disable all the Dout buffers of DRAM chips during the initial power-on period