用稳态反饱和吸收法测量C_（60）的激发态吸收截面

用准连续激光实现了Ｃ６０的稳态反饱和吸收，通过实验和理论计算的拟合，确定了Ｃ６０的三重第一激发态吸收截面。     

Modeling the I-V characteristics of fully depleted submicrometerSOI MOSFET's

In this paper, an analytic current-voltage model for submicrometer fully-depleted (FD) silicon-on-insulator (SOI) MOSFET's is presented. This model takes into account the source/drain series resistances which can be especially high in thin film SOI devices. The effect of drain induced conductivity enhancement is also included, which is important for submicrometer channels. The model is verified by comparison to measured SOI I-V characteristics. Good agreement is obtained for SOI film thicknesses ranging from 40 to 220 nm and effective channel lengths down to 0.25 μm     

Classification of pixels in a noisy grayscale image of polar ice

Often, in synthetic aperture radar (SAR) images of polar ice, one encounters shadow-like features across the images. Such features make it difficult to classify pixels into ice and water. Accordingly, it becomes a challenge to determine the true size and boundaries of ice floes in an SAR image of polar ice. We develop a simple statistical procedure which classifies pixels of an image by eliminating the effects of shadow-like features. Methodology developed in this paper is illustrated using some noisy SAR images of ice floes in the Arctic sea.     

A quadruple well, quadruple polysilicon BiCMOS process for fast 16Mb SRAM's

An advanced, high-performance, quadruple well, quadruple polysilicon BiCMOS technology has been developed for fast 16 Mb SRAM's. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 μm² with conventional I-line lithography and 7.32 μm² with I-line plus phase-shift or with deep UV lithography. The process features PELOX isolation to provide a 1.0 μm active pitch, MOSFET transistors designed for a 0.80 μm gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thin-film polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance     

A new MMIC broadside coupler using an array of air-bridges for directivity enhancement

A new quadrature broadside coupler is proposed, which employs an array of air-bridges to enhance directivity via its phase-equalization effect on the c-mode and /spl pi/-modes. The realization of air-bridges follows a standard MMIC fabrication process. An experimental chip fabricated on the 75-/spl mu/m GaAs substrate verifies the air-bridge effect and shows wideband characteristics of the coupling of 3.2/spl plusmn/0.4 dB, the insertion loss of 3.9/spl plusmn/0.4 dB, the output phase deviation from quadrature less than 6/spl deg/, and the isolation greater than 18 dB from 20 to 40 GHz.     

Test data compression and test time reduction using an embedded microprocessor

Systems-on-a-chip (SOCs) with many complex intellectual property cores require a large volume of data for manufacturing test. The computing power of the embedded processor in a SOC can be used to test the cores within the chip boundary, reducing the test time and memory requirements. This paper discusses techniques that use the computing power of the embedded processor in a more sophisticated way. The processor can generate and reuse random numbers to construct test patterns and selectively apply only those patterns that contribute to the fault coverage, significantly reducing the pattern generation time, the total number of test applications and, hence, the test time. It can also apply deterministic test patterns that have been compressed using the characteristics of the random patterns as well as those of the deterministic patterns themselves, which leads to high compression of test data. We compare three fast run-length coding schemes which are easily implemented and effective for test-data compression. We also demonstrate the effectiveness of the proposed approach by applying it to some benchmark circuits and by comparing it with other available techniques.     

A graphic approach to performance analysis of multistage linear interference canceller in long-code CDMA systems

The signal-to-interference-plus-noise-ratio performance of the multistage linear parallel and successive interference cancellers (LPIC and LSIC) in a long-code code-division multiple-access system is analyzed using a graphical approach. The decision statistic is modeled as a Gaussian random variable, whose mean and variance can be expressed as functions of moments of R for the LPIC and L for the LSIC, respectively, where R is the correlation matrix of signature sequences and L is the strict lower triangular part of R. Since the complexity of calculating these moments increases rapidly with the growth of the stage index, a graphical representation of moments is developed to facilitate the computation. Propositions are presented to relate the moment calculation problem to several well-known problems in graph theory, i.e., the coloring, the graph decomposition, the biconnected component finding, and the Euler tour problems. It is shown that the derived analytic results match well with simulation results.     

Monolithic SiGe Up‐/Down‐Conversion Mixers with Active Baluns

The purpose of this paper is to describe the implementation of monolithically matching circuits, interface circuits, and RF core circuits to the same substrate. We designed and fabricated on‐chip 1 to 6 GHz up‐conversion and 1 to 8 GHz down‐conversion mixers using a 0.8 µm SiGe hetero‐junction bipolar transistor (HBT) process technology. To fabricate a SiGe HBT, we used a reduced pressure chemical vapor deposition (RPCVD) system to grow a base epitaxial layer, and we adopted local oxidation of silicon (LOCOS) isolation to separate the device terminals. An up‐conversion mixer was implemented on‐chip using an intermediate frequency (IF) matching circuit, local oscillator (LO)/radio frequency (RF) wideband matching circuits, LO/IF input balun circuits, and an RF output balun circuit. The measured results of the fabricated up‐conversion mixer show a positive power conversion gain from 1 to 6 GHz and a bandwidth of about 4.5 GHz. Also, the down‐conversion mixer was implemented on‐chip using LO/RF wideband matching circuits, LO/RF input balun circuits, and an IF output balun circuit. The measured results of the fabricated down‐conversion mixer show a positive power conversion gain from 1 to 8 GHz and a bandwidth of about 4.5 GHz.     

Effects of α‐form or β‐form nuclei on polymorphic crystalline morphology of poly(butylene adipate)

The effects of α‐form and β‐form nuclei on polymorphic morphology of poly(butylene adipate) (PBA) upon recrystallization from the molten state up to various T_max values were examined by differential scanning calorimetry (DSC), wide‐angle X‐ray diffraction (WAXD) and polarized light microscopy (PLM). In this study, PBA with complex melting and polymorphism behaviour was used as a model for examining different types and extents of residual nuclei. As the PBA initially containing the sole α‐crystal was brought to a molten state of various T_max, the extents of trace α‐form crystal nuclei varied and were dependent on T_max. Furthermore, it did not matter whether, initially, the PBA contained α‐ or β‐form crystals (or both) because only a single type of α‐nuclei could be left upon treatment to the molten liquid state at T_max. Therefore, only the α‐crystal in PBA had ‘memory capacity’ in the molten liquid state while the β‐crystal did not. This was so because the latter had been completely transformed into the solid state prior to being heated into a liquid. PBA crystallized before α‐nuclei could be packed into α‐crystal, regardless of the crystallization temperature (T_c). For recrystallization from molten PBA without any nuclei, the crystalline polymorphism was correspondingly influenced by T_c. Copyright © 2005 Society of Chemical Industry