Deposition of carbon films by electrolysis of a water-ethylene glycol solution

An attempt was made to deposit carbon films by electrolysis of a water-ethylene glycol solution. Carbon plate and an n-type silicon substrate were dipped in the solution and a high d.c. potential was negatively applied on the silicon substrate. Some deposits were observed in the region between the boiling point curve and the line approximately 50 °C below and parallel to the boiling point, when electrolysis was carried out at 1 kV for 6 h. For higher potentials of 1.4–2.0 kV and longer electrolysis of 12 h, some samples showed a broad X-ray diffraction peak and Raman peaks, corresponding to graphitic carbon.     

Lubricant formulations with improved bioresistance

Translated from Khimiya i Tekhnologiya Topliv i Masel, No. 8, pp. 29–30, August, 1992.     

Prediction of axial velocity profiles and solids hold-up in a rotary kiln

Axial bed depth profiles were experimentally measured in a rotary kiln containing ilmenite particles under steady state and transient conditions. The variables include feed rate of solids, inclination and rotational speed of the kiln. and dam height. The variation of the axial velocity with kiln axis was estimated. The semi-experimental model proposed by Perron and Bui (1990) was modified to include the effect of the variables of the present study. The mean residence time of solids was estimated from the fractional hold-up and expressed in terms of the process variables. The transients induced by a step change in any of the operating conditions were measured as variation of discharge rate of solids with time.     

Some further observations on the differentiation method of modalreduction

The differentiation method of model reduction is shown to be equivalent to forming successive ratios of multipoint Taylor polynomial approximation of the numerator and denominator of the transfer function, respectively. This reformulation allows the method to be applied entirely through a Routh-type array structure. Strong links are seen to exist between the method and other stability preserving methods via this Routh-type structure     

Minimal communication cost software construction in the Internet environment

This paper investigates the issue of building software in the Internet environment, where local area network (LAN) based systems are interconnected by links with different bandwidth and do not share file systems. The software is modeled as a directed acyclic graph. Each node in the graph represents a logical step in processing the software while the edges describe the order of execution. The problem is to construct the software at a particular LAN with minimum Internet communication cost. An optimal polynomial algorithm, SOFTCON, with time complexity is presented, where and are the number of nodes and edges in the graph describing the software respectively, is the number of LANs in the Internet environment, and is the time complexity of the network flow algorithm on the flow network with nodes and edges transformed from the directed acyclic graph of the software. Received: 6 December 1995 / 1 May 1996     

Quasi-bound states determination using a perturbed wavenumbersmethod in a large quantum box

A perturbed wavenumbers method (PWM) is presented that is capable of determining the quasi-bound-state eigenenergies and their lifetimes for quantum heterostructures having arbitrary potential profiles. The numerical method presented solves the single-band effective-mass Schrodinger equation without using complex energies. It is applicable to quantum structures that are symmetric, asymmetric, unbiased, or biased. For multiple quantum heterostructures, extensive comparisons of this numerical method with other currently used techniques are included. In addition, a modified density of states formulation is presented and applied to these example cases     

A novel on-chip electrostatic discharge (ESD) protection withcommon discharge line for high-speed CMOS LSIs

A novel on-chip electrostatic discharge (ESD) protection for high-speed CMOS LSI's that operate at higher than 500 MHz has been developed. Introduction of a newly developed common discharge line (CDL) can completely eliminate the protection device influence on the inner circuit operation. This enables minimization of the I/O capacitance by shrinking the dimension of the output transistor, which also serves as a protection device in conventional devices. This new protection (CDL protection) was applied to a high-speed DRAM of which I/O pin capacitance specification is 2 pF. As a result, the ESD tolerance of 4 kV for the charged device model test, 4 kV for the human body model test, and 700 V for the machine model test were obtained. In addition, the DRAM data rate higher than 660 MHz at room temperature was achieved. The results show significant improvement for both ESD and the I/O capacitance, compared with the conventional structure     

Automated low-power technique exploiting multiple supply voltagesapplied to a media processor

This paper describes an automated design technique to reduce power by making use of two supply voltages. The technique consists of structure synthesis, placement, and routing. The structure synthesizer clusters the gates off the critical paths so as to supply the reduced voltage to save power. The placement and routing tool assigns either the reduced voltage or the unreduced one to each row so as to minimize the area overhead. The reduced supply, voltage is also exploited in a clock tree to reduce power. Combining these techniques together, we applied it to a media processor chip. The combined technique reduced the power by 47% in random-logic modules and by 73% in the clock tree, while keeping the performance