A 10-bit 205-MS/s 1.0- mm2 90-nm CMOS Pipeline ADC for Flat Panel Display Applications

This paper describes a 10-bit 205-MS/s pipeline analog-to-digital converter (ADC) for flat panel display applications with the techniques to alleviate the design limitations in the deep-submicron CMOS process. The switched source follower combined with a resistor-switch ladder eliminates the sampling switches and achieves high linearity for a large single-ended input signal. Multistage amplifiers adopting the complementary common-source topology increase the output swing range with lower transconductance variation and reduce the power consumption. The supply voltage for the analog blocks is provided by the low drop-out regulator for a high power-supply rejection ratio (PSRR) under the noisy operation environment. The pipeline stages of the ADC are optimized in the aspect of power consumption through the iterated calculation of the sampling capacitance and transconductance. The ADC occupies an active area of 1.0 mm² in a 90-nm CMOS process and achieves a 53-dB PSRR for a 100-MHz noise tone with the regulator and a 55.2-dB signal-to-noise-and-distortion ratio for a 30-MHz 1.0-V_PP single-ended input at 205 MS/s. The ADC core dissipates 40 mW from a 1.0-V nonregulated supply voltage.     

A Discrete‐Amplitude Pulse Width Modulation for a High‐Efficiency Linear Power Amplifier

A new discrete‐amplitude pulse width modulation (DAPWM) scheme for a high‐efficiency linear power amplifier is proposed. A radio frequency (RF) input signal is divided into an envelope and a phase modulated carrier. The low‐frequency envelope is modulated so that it can be represented by a pulse whose area is proportional to its amplitude. The modulated pulse has at least two different pulse amplitude levels in order that the duty ratios of the pulse are kept large for small input. Then, an RF pulse train is generated by mixing the modulated envelope with the phase modulated carrier. The RF pulse train is amplified by a switching‐mode power amplifier, and the original RF input signal is restored by a band pass filter. Because duty ratios of the RF pulse train are kept large in spite of a small input envelope, the DAPWM technique can reduce loss from harmonic components. Furthermore, it reduces filtering efforts required to suppress harmonic components. Simulations show that the overall efficiency of the pulsed power amplifier with DAPWM is about 60.3% for a mobile WiMax signal. This is approximately a 73% increase compared to a pulsed power amplifier with PWM.     

Virus‐Tethered Magnetic Gold Microspheres with Biomimetic Architectures for Enhanced Immunoassays

In immunoassays, non‐specific bindings to biosensing surfaces can be effectively prevented by formation of biocompatible and hydrophilic self‐assembled monolayer (SAM) on the surfaces. A thin gold (Au) layer on magnetic microspheres, 15 μm in diameter, enables facile SAM formation and thereby accepts second layer of filamentous virus scaffolds for the immobilization of functional proteins. The merger of the virus and SAM‐Au protected microspheres not only provides exceptionlly dense antibody loading, but also resembles biological cellular structures that enhance ligand‐receptor interactions. Site‐specific biotinylation of filamenous viruses allows formation of free‐standing virus threads (>1.0 × 10¹⁰) on streptavidin‐modified SAM‐Au microspheres. The augmented yield of antibody loading, due to the increased surface to volume ratio, on virus‐modified Au microspheres is confirmed by measuring fluorescence intensities. The bead‐based immunoassays for the detection of cardiac marker proteins exhibit increased sensitivity of virus‐Au microspheres, as low as 20 pg mL^?1 of cardiac troponin I in serum, and extremely low non‐specific adsorption when compared with bare polymer beads. This increased sensitivity due to filamentous morphology and SAM‐Au layer demonstrates the feasibility of merging viruses with non‐biological materials to yield biomimetic tools for the enhanced bead‐based immunoassays.     

Holography and plasma oxidation for uniform nanoscale two dimensional channel formation of vertical organic field-effect transistors with suppressed gate leakage current

Vertical organic field-effect transistors (VOFETs) with nanoscale channel openings have been fabricated using pentacene as an active layer material. To achieve uniform nanoscale two-dimensional channel openings, a laser holography lithography has been introduced. Uniformly distributed and well-aligned holes with 250 nm diameter were successfully obtained with the laser holography lithography. VOFET devices with these channel openings have shown high on/off ratio of about 10³ without any further treatment. Gate leakage current was also decreased with an additional insulating layer generated on the gate electrode sidewall via plasma oxidation.     

Photonic Crystal Palette of Binary Block Copolymer Blends for Full Visible Structural Color Encryption

Structural color (SC) arising from a periodically ordered self-assembled block copolymer (BCP) photonic crystal (PC) is useful for reflective-mode sensing displays owing to its capability of stimuli-responsive structure alteration. However, a set of PC inks, each providing a precisely addressable SC in the full visible range, has rarely been demonstrated. Here, a strategy for developing BCP PC inks with tunable structures is presented. This involves solution-blending of two lamellar-forming BCPs with different molecular weights. By controlling the mixing ratio of the two BCPs, a thin 1D BCP PC film is developed with alternating in-plane lamellae whose periodicity varies linearly from ≈46 to ≈91 nm. Subsequent preferential swelling of one-type lamellae with either solvent or non-volatile ionic liquid causes the photonic band gap of the films to red-shift, giving rise to full-visible-range SC correlated with the pristine nanostructures of the blended films in both liquid and solid states. The BCP PC palette of solution-blended binary solutions is conveniently employed in various coating processes, allowing facile development of BCP SC on the targeted surface. Furthermore, full-color SC paintings are realized with their transparent PC inks, facilitating low-power pattern encryption.     

Stretchable,Transparent Zinc Oxide Thin Film Transistors

Stretchable and transparent thin film transistors (TFTs) with intrisically brittle oxide semiconductors are built using a wavy structural configuration that can provide high flexibility and stretchability. After device fabrication procedures including high temperature annealing, the oxide semiconductor‐based TFT arrays can be transferred directly to plastic or rubber substrates, without an additional device process, using transfer printing methods. This procedure can avoid some of the thermal degradation problems associated with plastic or rubber substrates by separating them from the annealing procedure needed to improve the device performance. These design and fabrication methods offer the possibility of developing a new format of stretchable electronics.     

Performance of improved probabilistic location update scheme forcellular mobile networks

This paper suggests an improved probabilistic location update (IPLU) scheme for advanced cellular mobile networks. The location management cost with IPLU is analyzed, and various performance characteristics of IPLU are investigated. It is shown that IPLU has the parameter q that can be used as a control parameter to achieve the best performance when the unit location update cost (U) and the unit paging cost (P) are given. In addition, this paper provides some recommendable values of q in two cases, P>U and P⩽U. As a result, we demonstrate a merit of IPLU, that is, simple implementation with an acceptable performance level, especially, under the future cellular mobile network environments where a vast number of microcells/picocells exist and the relative user mobility is very high     

Novel ESD strategy for high voltage non-volatile programming pin application

This paper presents a novel ESD strategy for non-volatile memory (NVM) programming pin in a 0.13um/30V technology. Suggested scheme can provide not only a major current discharge path to protect the internal circuit from ESD damage but also a voltage clamping function to prevent the soft error of programmed data during the ESD event. It has been validated by TLP experiments and TCAD simulation.     

Meshing wireless personal area networks: Introducing IEEE 802.15.5

This article presents an overview of the IEEE project 802.15.5 that targets providing mesh capabilities to both high-rate and low-rate wireless personal area networks. Low-rate mesh is built on IEEE 802.15.4 MAC, while high-rate mesh utilizes IEEE 802.15.3 MAC. We seek to share our insights and motivations of the approach adopted in the major components of the standard instead of presenting a la carte items drawn in the specification. We hope this article helps readers of the 802.15.5 standard to better understand the rationale and intent of the protocol design.