Presenting information on the small-screen interface: effects of table formatting

This study explored strengths and limitations of table formatting choices by engaging twenty-eight participants in information searches in online tables, presented on a small-screen interface (Palm IIIc). Table length across conditions was held constant at three screens long (24 rows total) but varied from one to three screens wide (approximately 35, 70, and 105 characters per line). Target information was positioned in either the upper left, lower left, upper right, or lower right quadrants. Data collected were time on task, error rate, and level of participants' confidence in their answers. Experimenters found that increased horizontal scrolling imposed the heaviest burden on information search. This study supports restricting table widths to one screen on handheld computers. If necessary, however, tables can go to two screens wide without critical detriment to usability. While ruled line formatting is slightly better than interface character in providing visual support for the burden of horizontal scrolling, neither formatting option adequately compensates for the added burden.     

Training ratio and comparison of trained vector quantizers

The vector quantizer (VQ) codebook is usually designed by clustering a training sequence (TS) drawn from the underlying distribution function. In order to cluster a TS, we may use the K-means algorithm (generalized Lloyd (1982) algorithm) or the self-organizing map algorithm. In this paper, a survey of trained VQ performance is conducted to study the effect of the training ratio on training quantizers. The training ratio, which is defined by the ratio of the TS size to the codebook size, is dependent on the VQ structure. Hence, different VQs may show different training properties, even though the VQs are designed for the same TS. A numerical comparison of trained VQs is then conducted in conjunction with deriving their training ratios. Through the comparison, it is shown that structured VQs can achieve better performance than the full-search scheme if the codebooks are trained by a finite TS. Further, we can derive a design or comparison guideline that maintains equal training ratios in training different VQs.     

QoS provisioning in cellular networks based on mobility prediction techniques

In cellular networks, QoS degradation or forced termination may occur when there are insufficient resources to accommodate handoff requests. One solution is to predict the trajectory of mobile terminals so as to perform resource reservations in advance. With the vision that future mobile devices are likely to be equipped with reasonably accurate positioning capability, we investigate how this new feature may be used for mobility predictions. We propose a mobility prediction technique that incorporates road topology information, and describe its use for dynamic resource reservation. Simulation results are presented to demonstrate the improvement in reservation efficiency compared with several other schemes.     

Origin of the threshold voltage instability in SiO/sub 2//HfO/sub 2/ dual layer gate dielectrics

The magnitude of the V/sub T/ instability in conventional MOSFETs and MOS capacitors with SiO/sub 2//HfO/sub 2/ dual-layer gate dielectrics is shown to depend strongly on the details of the measurement sequence used. By applying time-resolved measurements (capacitance-time traces and charge-pumping measurements), it is demonstrated that this behavior is caused by the fast charging and discharging of preexisting defects near the SiO/sub 2//HfO/sub 2/ interface and in the bulk of the HfO/sub 2/ layer. Based on these results, a simple defect model is proposed that can explain the complex behavior of the V/sub T/ instability in terms of structural defects as follows. 1) A defect band in the HfO/sub 2/ layer is located in energy above the Si conduction band edge. 2) The defect band shifts rapidly in energy with respect to the Fermi level in the Si substrate as the gate bias is varied. 3) The rapid energy shifts allows for efficient charging and discharging of the defects near the SiO/sub 2//HfO/sub 2/ interface by tunneling.     

Effect of exponentially graded base doping on the performance ofGaAs/AlGaAs heterojunction bipolar transistors

The authors have fabricated n-p-n GaAs/AlGaAs heterojunction bipolar transistors (HBTs) with base doping graded exponentially from 5×10¹⁹ cm^-3 at the emitter edge to 5×10¹⁸ cm^-3 at the collector edge. The built-in field due to the exponentially graded doping profile significantly reduces base transit time, despite bandgap narrowing associated with high base doping. Compared to devices with the same base thickness and uniform base doping of 1×10¹⁹ cm^-3 , the cutoff frequency is increased from 22 to 31 GHz and maximum frequency of oscillation is increased from 40 to 58 GHz. Exponentially graded base doping also results ill consistently higher common-emitter current gain than uniform base doping, even though the Gummel number is twice as high and the base resistance is reduced by 40%     

Rotative quadrature phase-shift keying

A rotative quadrature phase-shift keying (RQPSK) modulation scheme is proposed. By rotating the QPSK signal constellation by pi /2 either clockwise or anticlockwise during a symbol duration, the conventional QPSK scheme can be modified to transmit 3 bits per symbol to achieve both power and bandwidth efficiency.<>     

Vibration control of a flexible structure using a hybrid mount

This paper presents vibration control of a flexible beam structure using a hybrid mount which consists of elastic rubber and piezoelectric stack actuator. After identifying stiffness and damping properties of the rubber and piezoelectric elements, a mechanical model of the hybrid mount is established. The mount model is then incorporated with the beam structure, and the governing equation of motion is obtained in a state space. A sliding mode controller is designed in order to actively attenuate the vibration of the beam structure subjected to high-frequency and small magnitude excitations. The controller is experimentally realized and measured control responses such as acceleration of the beam structure and force transmission through the hybrid mount are evaluated and presented in both frequency and time domains.     

A high-capacity broadband packet switch architecture based on a multilink approach

Broadband packet networks based on asynchronous transfer mode (ATM) are expected to provide a wide range of services, including motion video, voice, data and image. When these networks become prevalent, some applications such as motion video and high-speed LAN interconnections will place a very large bit rate requirement on the channels. Currently, the physical layer supported by the synchronous optical network (SONET) allows the transmission of up to 2.4 Gbit/s with the OC-48 optical interface. However, it is not feasible for the electronic packet switch to route packets at this rate on a single link. In this paper we present a design of a broadband packet switch that uses multiple links in parallel to realize a high-speed channel. This implementation permits the switch to operate at the lower link rate, which can be at 150 Mbit/s, while having the ability to support a virtual circuit at a higher rate (up to 2.4 Gbit/s). The main contribution of the design is that packet sequence on a channel is still maintained even though packets are allowed to use any of the links belonging to the same channel. Besides allowing the switch to function at a slower rate than the transmission channel rate, the implementation of the multilinks benefits from statistical multiplexing gain. Analytical results show the performance advantages of multilink design with respect to delay, throughput and packet loss probability.     

89-GHz fT room-temperature silicon MOSFETs

The authors report the implementation of deep-submicrometer Si MOSFETs that at room temperature have a unity-current-gain cutoff frequency (f_T) of 89 GHz, for a drain-to-source bias of 1.5 V, a gate-to-source bias of 1 V, a gate oxide thickness of 40 Å, and a channel length of 0.15 μm. The fabrication procedure is mostly conventional, except for the e-beam defined gates. The speed performance is achieved through an intrinsic transit time of only 1.8 ps across the active device region     

A practical SPICE model based on the physics and characteristics of realistic single-electron transistors

A practical model for a single-electron transistor (SET) was developed based on the physical phenomena in realistic Si SETs, and implemented into a conventional circuit simulator. In the proposed model, the SET current calculated by the analytic model is combined with the parasitic MOSFET characteristics, which have been observed in many recently reported SETs formed on Si nanostructures. The SPICE simulation results were compared with the measured characteristics of the Si SETs. In terms of the bias, temperature, and size dependence of the realistic SET characteristics, an extensive comparison leads to good agreement within a reasonable level of accuracy. This result is noticeable in that a single set of model parameters was used, while considering divergent physical phenomena such as the parasitic MOSFET, the Coulomb oscillation phase shift, and the tunneling resistance modulated by the gate bias. When compared to the measured data, the accuracy of the voltage transfer characteristics of a single-electron inverter obtained from the SPICE simulation was within 15%. This new SPICE model can be applied to estimating the realistic performance of a CMOS/SET hybrid circuit or various SET logic architectures.