Magnet Safety Assessment for ITER

The ITER magnet system consists of structurally linked sets of toroidal (TF) and poloidal (PF) field coils, central solenoid (CS), and various support structures. The coils are superconducting, force flow Helium cooled with a Kapton-Glass-Epoxy multilayer insulation system. The stored magnetic energy is about 100GJ in the TF system and 20GJ in the PF-CS. Coils and structure are maintained at 4 K by enclosing them in a vacuum cryostat. The cryostat, comprising an outer envelope to the magnets, forms most of the second radioactivity confinement barrier. The inner primary barrier is formed by the vacuum vessel, its ports and their extensions. To keep the machine size within acceptable bounds, it is essential that the magnets are in close proximity to both of the nuclear confinement barriers. The objective of the magnet design is that, although local damage to one of the barriers may occur in very exceptional circumstances, large scale magnet structural or thermal failure leading to simultaneous breaching of both barriers is not credible. Magnet accidents fall into three categories: thermal (which includes arcing arising from insulation failure and local overheating due to discharge failure in the event of a superconductor quench), structural (which includes component mechanical failure arising from material inadequacies, design errors and exceptional force patterns arising from coil shorts or control failures), and fluid (Helium release due to cooling line failure). After a preliminary survey to select initial faults conceivable within the present design, these faults are systematically analyzed to provide an assessment of the damage potential. The results of this damage assessment together with an assessment of the reliability of the monitoring and protective systems, shows that the magnets can operate with the required safety condition.     

Design and performance evaluation of a banyan network basedinterconnection structure for ATM switches

This paper presents a new self-routing packet network called the plane interconnected parallel network (PIPN). In the proposed design, the traffic arriving at the network is shaped and routed through two banyan network based interconnected planes. The interconnections between the planes distribute the incoming load more homogeneously over the network. The throughput of the network under uniform and heterogeneous traffic requirements is studied analytically and by simulation. The results are compared with the results of the baseline network and another banyan network based parallel interconnection network. It is shown that, for the proposed design, a higher degree of heterogeneity results in better performance     

Positive temperature dependence of the electron impact ionizationcoefficient in In0.53Ga0.47As/InP HBTs

Impact ionization is a major limiting factor to the maximum operating voltage of InGaAs-based, high-speed transistors. In this work, data on the positive temperature dependence of the electron impact ionization coefficient α_n in In_0.53Ga_0.47As at medium-low electric fields are reported for the first time. The increase of α_n with temperature is opposite to the behavior normally observed in most semiconductors. This anomalous behavior implies the onset of a positive feedback between power dissipation and avalanche generation which may adversely affect the power handling capability of In_0.53Ga _0.47As-based devices, and which should be taken into account in device thermal modeling. In the experimental procedure, based on the measurement of the multiplication factor M-1 in npn In_0.53Ga _0.47As/InP Heterojunction Bipolar Transistors (HBT), particular care has been taken in order to rule out possible spurious, temperature-dependent contributions to the measured multiplication current     

C-t analysis of MOS capacitors under constant current stress

The effect of high oxide field stress is studied using capacitance-time (C-t) measurements of MOS capacitors. The stress results in parallel shifts of the C-t curve along the time axis. The flatband voltage shift ΔV_FB obtained from the initial deep depletion capacitance C(t=0⁺) follows the same trend as that from the high-frequency C-V characteristics. However, the discrepancy between the two flatband voltages becomes larger as the stress increases due to the effect of interface charges on C-t characteristics. The flatband voltage difference is converted to interface trap density, showing a steady increase of interface trap density with stress, similar to that from low-frequency C-V measurements     

A fully soft-switched extended-period quasi-resonantpower-factor-correction circuit

This paper presents the design criteria, procedure, and implementation of a soft-switched power-factor-correction (PFC) circuit based on the extended-period quasi-resonant (EPQR) principles. All power electronic devices including switches and diodes in the circuit are fully soft switched. The design method is demonstrated in a prototype circuit. The operating principles are confirmed with computer simulation and experimental results. A comparison of the EP-QR operation and zero-voltage-transition (ZVT) pulse-width modulation (PWM) method     

A new lateral MOS-gated thyristor with controlling base-current

A new lateral MOS-gated thyristor, called the Base-Current-Controlled Thyristor, is described. This device is designed so that most holes at the on-stage reach the P base through the floating P⁺ region adjacent to the P base and the on-state MOSFET. At the turn-off stage, the interruption of the hole current to the P base due to switching off the above MOSFET occurs simultaneously with the conventional turn-off operation. The concept of this device is verified experimentally by using the fabricated lateral device with the external MOSFET. This device exhibits a better trade-off relation between the on-state voltage and the turn-off time compared uith the conventional MOS-gated thyristor     

Series equivalence/operation of current-controlled boost-typesingle-phase voltage source converters for bidirectional power flow

Single-phase voltage source power converters (VSCs) under consideration are AC-DC current-controlled boost-type power converters with bidirectional power-handling capability. Equivalence between two series-connected two-level power converters and a single three-level power converter is considered here. Further considered is the series operation of three-level power converters. Simulation results and experimental verification for both are provided. Economical configurations of three-level power converters leading to multilevel waveforms are presented thereafter     

A wafer level monitoring method for plasma-charging damage usingantenna PMOSFET test structure

A novel monitoring method for plasma-charging damage is proposed. This method performs a quick and accurate evaluation using antenna PMOSFET. It was found that not only hot-carrier (HC) lifetime but transistor parameters such as initial gate current and substrate current were changed according to the degree of plasma-charging damage. However, the present work suggests that monitoring the shift of drain current after a few seconds of HC stress is a more accurate method to indicate plasma-charging damage. The monitoring method using the present test structure is demonstrated to be useful for realizing highly reliable devices