Synthesis of Rice Processing Plants. I. Development of Simplified Models

This article, the first of three articles on the synthesis of rice processing plants, focuses on the development of simplified mathematical models necessary for use in optimizing rice processing plants. The second concentrates on the optimal synthesis of a rice plant and the third on the sensitivity of the optimization to uncertainty in model parameters. Existing models for rice processing unit operations are not suitable for flowsheet optimization and new models need to be developed to overcome numerical difficulties that occur in optimization applications, specifically in mixed integer nonlinear programming (MINLP) applications. Simplified models of the drying, cooling, and tempering units are developed. In addition head rice yield models, used as a quality indicator, energy consumption, and economic models were also developed. Naturally, the new models exhibit some mismatch with respect to the existing models from which they were developed. However, a sensitivity analysis, presented in Part III, has shown that the optimal flowsheet structure was not sensitive to a lack of fit between the simplified and complex models. The simplified models were found adequate to be appropriate for use at the synthesis stage.     

1/f noise in large-area Hg<Subscript>1−x</Subscript>Cd<Subscript>x</Subscript>Te photodiodes

The 1/f noise in photovoltaic (PV) molecular-beam epitaxy (MBE)-grown Hg_1−xCd_xTe double-layer planar heterostructure (DLPH) large-area detectors is a critical noise component with the potential to limit sensitivity of the cross-track infrared sounder (CrIS) instrument. Therefore, an understanding of the origins and mechanisms of noise currents in these PV detectors is of great importance. Excess low-frequency noise has been measured on a number of 1000-μm-diameter active-area detectors of varying “quality” (i.e., having a wide range of I-V characteristics at 78 K). The 1/f noise was measured as a function of cut-off wavelength under illuminated conditions. For short-wave infrared (SWIR) detectors at 98 K, minimal 1/f noise was measured when the total current was dominated by diffusion with white noise spectral density in the mid-10⁻¹⁵A/Hz^1/2 range. For SWIR detectors dominated by other than diffusion current, the ratio, α, of the noise current in unit bandwidth i_n(f = 1 Hz, V_d = −60 mV, and Δf = 1 Hz) to dark current I_d(V_d = −60 mV) was α_SW-d = i_n/I_d ∼ 1 × 10⁻³. The SWIR detectors measured at 0 mV under illuminated conditions had median α_SW-P = i_n/I_ph ∼ 7 × 10⁻⁶. For mid-wave infrared (MWIR) detectors, α_MW-d = i_n/I_d ∼ 2 × 10⁻⁴, due to tunneling current contributions to the 1/f noise. Measurements on forty-nine 1000-μm-diameter MWIR detectors under illuminated conditions at 98 K and −60 mV bias resulted in α_MW-P = i_n/I_ph = 4.16 ± 1.69 × 10⁻⁶. A significant point to note is that the photo-induced noise spectra are nearly identical at 0 mV and 100 mV reverse bias, with a noise-current-to-photocurrent ratio, α_MW-P, in the mid 10⁻⁶ range. For long-wave infrared (LWIR) detectors measured at 78 K, the ratio, α_LW-d = i_n/I_d ∼ 6 × 10⁻⁶, for the best performers. The majority of the LWIR detectors exhibited α_LW-d on the order of 2 × 10⁻⁵. The photo-induced 1/f noise had α_LW-P = i_n/I_ph ∼ 5 × 10⁻⁶. The value of the noise-current-to-dark-current ratio, α appears to increase with increasing bandgap. It is not clear if this is due to different current mechanisms impacting 1/f noise performance. Measurements on detectors of different bandgaps are needed at temperatures where diffusion current is the dominant current. Excess low-frequency noise measurements made as a function of detector reverse bias indicate 1/f noise may result primarily from the dominant current mechanism at each particular bias. The 1/f noise was not a direct function of the applied bias.     

Evaluation and optimization of package processing and design through solder joint profile prediction

Solder joints are generated using a variety of methods to provide both mechanical and electrical connection for applications such as flip-chip, wafer level packaging, fine pitch, ball-grid array, and chip scale packages. Solder joint shape prediction has been incorporated as a key tool to aid in process development, wafer level and package level design and development, assembly, and reliability enhancement. This work demonstrates the application of an analytical model and the Surface Evolver software in analyzing a variety of solder processing methods and package types. Bump and joint shape prediction was conducted for the design of wafer level bumping, flip-chip assembly, and wafer level packaging. The results from the prediction methodologies are validated with experimentally measured geometries at each level of design.     

Synthesis of ZSM‐5 Films and Monoliths with Bimodal Micro/Mesoscopic Structures

A route to synthesize ZSM‐5 crystals with a bimodal micro/mesoscopic pore system has been developed in this study; the successful incorporation of the mesopores within the ZSM‐5 structure was performed using tetrapropylammonium hydroxide (TPAOH)‐impregnated mesoporous materials containing carbon nanotubes in the pores, which were encapsulated in the ZSM‐5 crystals during a solid rearrangement process within the framework. Such mesoporous ZSM‐5 zeolites can be readily obtained as powders, thin films, or monoliths.     

An original approximate method for estimating the invariant probability distribution of a large class of multi-dimensional nonlinear stochastic oscillators

This paper proposes an original method for obtaining analytical approximations of the invariant probability density function of multi-dimensional Hamiltonian dissipative dynamic systems under Gaussian white noise excitations, with linear non-conservative parts and nonlinear conservative parts. The method is based on an exact result and a heuristic argument. Its pertinence is attested by numerical tests.     

Derivation of a second-order switching surface in the boundary control of buck converters

A second-order switching surface in the boundary control of buck converters is derived in this letter. The formulated switching surface can make the overall converter exhibit better steady-state and transient behaviors than the one with a first-order switching surface. The switching surface is derived by estimating the state trajectory movement after a switching action, resulting in a high state trajectory velocity along the switching surface. This phenomenon accelerates the trajectory moving toward the target operating point. The proposed control scheme has been successfully applied to a 120-W buck converter. The large-signal performance and a comparison with the first-order switching surface have been studied.     

Influence of device engineering on the analog and RF performances of SOI MOSFETs

This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).     

On the physical and logical topology design of large-scale optical networks

We consider the problem of designing a network of optical cross-connects (OXCs) to provide end-to-end lightpath services to large numbers of label switched routers (LSRs). We present a set of heuristic algorithms to address the combined problem of physical topology design (i.e., determine the number of OXCs required and the fiber links among them) and logical topology design (i.e., determine the routing and wavelength assignment for the lightpaths among the LSRs). Unlike previous studies which were limited to small topologies with a handful of nodes and a few tens of lightpaths, we have applied our algorithms to networks with hundreds or thousands of LSRs and with a number of lightpaths that is an order of magnitude larger than the number of LSRs. In order to characterize the performance of our algorithms, we have developed lower bounds which can be computed efficiently. We present numerical results for up to 1000 LSRs and for a wide range of system parameters such as the number of wavelengths per fiber, the number of transceivers per LSR, and the number of ports per OXC. The results indicate that it is possible to build large-scale optical networks with rich connectivity in a cost-effective manner, using relatively few but properly dimensioned OXCs.     

Static energy reduction techniques for microprocessor caches

Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of static energy consumption due to subthreshold leakage current in cache memory arrays. This paper compares three techniques for reducing static energy consumption in on-chip level-1 and level-2 caches. One technique employs low-leakage transistors in the memory cell. Another technique, power supply switching, can be used to turn off memory cells and discard their contents. A third alternative is dynamic threshold modulation, which places memory cells in a standby state that preserves cell contents. In our experiments, we explore the energy and performance tradeoffs of these techniques. We also investigate the sensitivity of microprocessor performance and energy consumption to additional cache latency caused by leakage-reduction techniques.