Antenna design strategy and demonstration for software-defined radio (SDR)

Antennas are a key enabling technology for software-defined radio (SDR). Although software is extremely flexible, SDR??s potential is limited by antenna size and performance. In this paper, we review typical antenna miniaturization techniques and fundamental theories that limit antenna size and performance including operational bandwidth, gain (or range), and radiation pattern. Possible antenna design strategies are discussed to meet the desired specifications in SDR based on observations from the limit theories. The application of strategies to enable multiband (resonant), continuous multiband (frequency independent), and instantaneous, ultra-wideband antennas are discussed qualitatively. Advantages, disadvantages, and design trade-off strategies for different types of antennas are compared from a system-level perspective. A design example for a compact ultra-wideband (UWB) antenna is presented for a software-defined platform. The example involves a direct-conversion radio developed in Wireless@VT that uses a Motorola RFIC having a 100 MHz?C6 GHz operational frequency range with a 9 kHz?C20 MHz channel bandwidth. The example antenna covers frequencies from 450 MHz to 6 GHz instantaneously with approximately 5-dBi realized gain over a finite-size ground plane, including return loss and omni-directional coverage.     

News: EPA report targets 10 key research areas

Science.     

Modeling Energy Recovery Using Thermoelectric Conversion Integrated with an Organic Rankine Bottoming Cycle

Engine and industrial waste heat are sources of high-grade thermal energy that can potentially be utilized. This paper describes a model system that employs thermoelectric conversion as a topping cycle integrated with an organic Rankine bottoming cycle. The model has many parameters that define combined system quantities such as overall output power and conversion efficiency. The model can identify the optimal performance points for both the thermoelectric and organic Rankine bottoming cycle. Key analysis results are presented showing the impact of critical design parameters on power output and system performance.     

系统级封装技术及其应用

本文介绍了系统级封装技术及其兴起背景,对比了与SoC的异同。通过分析系统级封装的技术特点,阐述了其优势;分析了系统级封装的成本构成和特点。本文从集成电路产业链整合的观点,分析了国内系统级封装的机遇与挑战;以长电科技为例,介绍了系统级封装在设计、制造上的关键技术与当前的能力,并分析了未来的趋势和挑战。本丈还对当前的系统级封装产品与应用领域做了详细介绍。     

固态源输运系统推动铪基栅介质的应用

在生产中引入高介电常数绝缘材料/金属栅电极结构,需要采用全新的制造技术,前驱物和输运系统推动了铪基材料栅极绝缘层的应用。AID技术也促进了新一代栅电极材料的推广和应用。     

LabVIEW8．5为开发者带来多核处理器的强大功能

根据摩尔定律,芯片上晶体管的数目每隔18～24个月就会翻一番。如同在过去40年里一样,这个定律现在还是正确的,但是在性能上却并不再呈现一个线性增强的现象。以前,芯片制造商通过提高处理器时钟速度使芯片性能翻番——从100MHz到200MHz,直至近来达到吉赫兹。     

Low-Power Parallel Video Compression Architecture for a Single-Chip Digital CMOS Camera

A low-power, large-scale parallel video compression architecture for a single-chip digital CMOS camera is discussed in this paper. This architecture is designed for highly computationally intensive image and video processing tasks necessary to support video compression. Two designs of this architecture, an MPEG2 encoder and a DV encoder, are presented. At an image resolution of 640 × 480 pixels (MPEG2) and 720 × 576 (DV) and a frame rate of 25 to 30 frames per second, a computational throughput of up to 1.8 billion operations per second (BOPS) is required. This is supported in the proposed architecture using a 40 MHz clock and an array of 40 to 45 parallel processors implemented in a 0.2 m CMOS technology and with a 1.5 V supply voltage. Power consumption is significantly reduced through the single-chip integration of the CMOS photo sensors, the embedded DRAM technology, and the proposed pipelined parallel processors. The parallel processors consume approximately 45 mW of power resulting a power efficiency of 40 BOPS/W.