Modern development methods and tools for embedded reconfigurable systems: A survey

Heterogeneous reconfigurable systems provide drastically higher performance and lower power consumption than traditional CPU-centric systems. Moreover, they do it at much lower costs and shorter times to market than non-reconfigurable hardware solutions. They also provide the flexibility that is often required for the engineering of modern robust and adaptive systems. Due to their heterogeneity, flexibility and potential for highly optimized application-specific instantiation, reconfigurable systems are adequate for a very broad class of applications across different industry sectors. What prevents the reconfigurable system paradigm from a broad proliferation is the lack of adequate development methodologies and electronics design tools for this kind of systems. The ideal would be a seamless compilation of a high-level computation process specification into an optimized mixture of machine code executed on traditional CPU-centric processors and on the application-specific decentralized parallel data-flow-dominated reconfigurable processors and hardware accelerators. Although much research and development in this direction was recently performed, the adequate methodologies and tools necessary to implement this compilation process as an effective and efficient hardware/software co-synthesis flow are unfortunately not yet in place. This paper focuses on the recent developments and development trends in the design methods and synthesis tools for reconfigurable systems. Reconfigurable system synthesis performs two basic tasks: system structure construction and application process mapping on the structure. It is thus more complex than standard (multi-)processor-based system synthesis for software-programmable systems that only involves application mapping. The system structure construction may involve the macro-architecture synthesis, the micro-architecture synthesis, and the actual hardware synthesis. Also, the application process mapping can be more complicated and dynamic in reconfigurable systems. This paper reviews the recent methods and tools for the macro- and micro-architecture synthesis, and for the application mapping of reconfigurable systems. It puts much attention to the relevant and currently hot topic of (re-)configurable application-specific instruction set processors (ASIP) synthesis, and specifically, ASIP instruction set extension. It also discusses the methods and tools for reconfigurable systems involving CPU-centric processors collaborating with reconfigurable hardware sub-systems, for which the main problem is to decide which computation processes should be implemented in software and which in hardware, but the hardware/software partitioning has to account for the hardware sharing by different computation processes and for the reconfiguration processes. The reconfigurable system area is a very promising, but quite a new field, with many open research and development topics. The paper reviews some of the future trends in the reconfigurable system development methods and tools. Finally, the discussion of the paper is summarized and concluded.     

A Perspective Review of Security Challenges in Body Area Networks for Healthcare Applications

International Journal of Wireless Information Networks - Body area network (BAN) connects sensors and actuators to the human body in order to collect patient’s information and transmitting it...     

Gaussianization: An Efficient Multivariate Density Estimation Technique for Statistical Signal Processing

Multivariate density estimation is an important problem that is frequently encountered in statistical learning and signal processing. One of the most popular techniques is Parzen windowing, also referred to as kernel density estimation. Gaussianization is a procedure that allows one to estimate multivariate densities efficiently from the marginal densities of the individual random variables. In this paper, we present an optimal density estimation scheme that combines the desirable properties of Parzen windowing and Gaussianization, using minimum Kullback–Leibler divergence as the optimality criterion for selecting the kernel size in the Parzen windowing step. The utility of the estimate is illustrated in classifier design, independent components analysis, and Prices’ theorem.     

Ytterbium-Doped P$_2$O$_5$-TeO $_2$ Glass for Laser Applications

Ytterbium-doped sodium phospho-tellurite glasses are made with different P₂O₅:TeO₂ ratio, and Yb³⁺ concentrations. Physical properties of the new Yb hosts are favorable for laser applications. The glasses show high absorption and emission cross sections and higher lifetime of Yb³⁺:²F_5/2rarr²F_7/2 transition. The emission cross sections are calculated using two different methods and compared. The laser parameters of these Yb³⁺ -doped glasses are better than many reported glasses and crystals making them potential to fabricate high power laser and broadband optical amplifier in the wavelength region around ~1 mum     

Editorial: Security and Privacy in Internet of Things

Mobile Networks and Applications -     

The muscle activation method: an approach to impedance control of brain-machine interfaces through a musculoskeletal model of the arm

Current demonstrations of brain-machine interfaces (BMIs) have shown the potential for controlling neuroprostheses under pure motion control. For interaction with objects, however, pure motion control lacks the information required for versatile manipulation. This paper investigates the idea of applying impedance control in a BMI system. An extraction algorithm incorporating a musculoskeletal arm model was developed for this purpose. The new algorithm, called the muscle activation method (MAM), was tested on cortical recordings from a behaving monkey. The MAM was found to predict motion parameters with as much accuracy as a linear filter. Furthermore, it successfully predicted limb interactions with novel force fields, which is a new and significant capability lacking in other algorithms.     

在数字基带处理器上代码的最佳放置

在手机等嵌入式系统中,除了处理器执行时间外,最重要的资源就是设备总线和存储器接口。本文将介绍一种在使用指令高速缓存时其带宽消耗的基础上,统计分析高速缓存所采用的方法。这种方法是传统基于指令周期的分析方法的补充,并且也为在外部存储接口受限制的设备中优化应用程序提供了一种手段。在外部接口受限制的设备中优化那些使用高速缓存的应用程序的读取带宽,对提升指令周期性能有着良好效果。作为例子,     

A novel CMOS exponential transconductor operating in weak inversion

A novel CMOS exponential transconductor which employs only three NMOS transistors operating in weak inversion, is presented. The main advantage of the proposed circuit is its wide range of exponential behaviour, which reaches up to five decades of current range, and above 10 μA to an input voltage range of 800 mV. The physical realisation is achieved in two forms: in the first one, the circuit is implemented with discrete MOS transistor arrays by CD4007 series; in the second one, the circuit is fully integrated in a 0.5 μm CMOS standard process. Simulated and experimental results of the proposed exponential transconductor are also presented.     

3D Printing of a Thermo‐ and Solvatochromic Composite Material Based on a Cu(II)–Thymine Coordination Polymer with Moisture Sensing Capabilities

This work presents the fabrication of 3D‐printed composite objects based on copper(II) 1D coordination polymer ( CP1 ) decorated with thymine along its chains with potential utility as an environmental humidity sensor and as a water sensor in organic solvents. This new composite object has a remarkable sensitivity, ranging from 0.3% to 4% of water in organic solvents. The sensing capacity is related to the structural transformation due to the loss of water molecules that CP1 undergoes with temperature or by solvent molecules' competition, which induces significant change in color simultaneously. The CP1 and 3D printed materials are stable in air over 1 year and also at biological pHs (5–7), therefore suggesting potential applications as robust colorimetric sensors. These results open the door to generate a family of new 3D printed materials based on the integration of multifunctional coordination polymers with organic polymers.