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11.
Recently, it was demonstrated that the expression of BMAL1 was decreased in the endometrium of women suffering from recurrent spontaneous abortion. To investigate the pathological roles of uterine clock genes during pregnancy, we produced conditional deletion of uterine Bmal1 (cKO) mice and found that cKO mice could receive embryo implantation but not sustain pregnancy. Gene ontology analysis of microarray suggested that uterine NK (uNK) cell function was suppressed in cKO mice. Histological examination revealed the poor formation of maternal vascular spaces in the placenta. In contrast to WT mice, uNK cells in the spongiotrophoblast layer, where maternal uNK cells are directly in contact with fetal trophoblast, hardly expressed an immunosuppressive NK marker, CD161, in cKO mice. By progesterone supplementation, pregnancy could be sustained until the end of pregnancy in some cKO mice. Although this treatment did not improve the structural abnormalities of the placenta, it recruited CD161-positive NK cells into the spongiotrophoblast layer in cKO mice. These findings indicate that the uterine clock system may be critical for pregnancy maintenance after embryo implantation.  相似文献   
12.
A full-color twisted-nematic type liquid crystal display (TN-LCD) of 1.4-in diagonal size driven by organic thin-film transistors (TFTs) has been fabricated. This TN-LCD has 80/spl times/80/spl times/3 (RGB) pixel arrays addressed by pentacene TFTs with a channel width of 50 /spl mu/m. The contact resistance between the pentacene film and the source/drain electrodes has been reduced by selecting the exposure condition of the photoresist in patterning the electrodes. In addition, a solution-processed passivation film with a novel structure, consisting of photosensitive polyvinylalcohol and organosiloxane glass resin, has been developed to protect the TFTs against degradation induced by integration with TN-LCD devices. Consequently, it has been confirmed that the organic-TFT-driven TN-LCD fabricated in this paper is capable of displaying full-color moving images at a resolution of 80 pixels per inch.  相似文献   
13.
The performance of discrete-Fourier-transform (DFT)-based velocity estimators for wind-sensing coherent Doppler lidar systems in the Kolmogorov turbulence regime is summarized using Monte Carlo simulations. Furthermore, a signal model, a simulation procedure, velocity estimators, and simulation conditions are explained. The relationships between signal-to-noise ratio, line-of-sight velocity estimation precision, and signal detection probability are simulated and summarized. In addition to the basic DFT estimator, signal matching estimators which utilize DFT are studied. The performances in the Kolmogorov turbulence regime and those in the Gaussian autocovariance signal model are compared. The performances are compared for wavelength regions of 1.5, 2, and 10 mum.  相似文献   
14.
The effects of the proximity contact with magnetic insulator on the spin‐dependent electronic structure of graphene are explored for the heterostructure of single‐layer graphene (SLG) and yttrium iron garnet Y3Fe5O12 (YIG) by means of outermost surface spin spectroscopy using a spin‐polarized metastable He atom beam. In the SLG/YIG heterostructure, the Dirac cone electrons of graphene are found to be negatively spin polarized in parallel to the minority spins of YIG with a large polarization degree, without giving rise to significant changes in the π band structure. Theoretical calculations reveal the electrostatic interfacial interactions providing a strong physical adhesion and the indirect exchange interaction causing the spin polarization of SLG at the interface with YIG. The Hall device of the SLG/YIG heterostructure exhibits a nonlinear Hall resistance attributable to the anomalous Hall effect, implying the extrinsic spin–orbit interactions as another manifestation of the proximity effect.  相似文献   
15.
16.
本文论述一种厚/薄铜复合PWB(及其可靠性),它允许PWB设计者在厚铜和薄铜之间以任何希望的图形进行随意选择,以使电源模块/分配电路可以和精细图形特征一起集成,从而适应离I/O数半导体封装的要求。  相似文献   
17.
A single-ended amplifier using small packaged GaN-FETs exhibits a record 2.14 GHz W-CDMA output power. The amplifier, composed of paralleled 48 mm gate periphery FET die, delivers a peak saturated output power of 371 W with a linear gain of 11.2 dB at a drain voltage of 45 V under 2.14 GHz 3GPP W-CDMA signal input. The output power density (output power/package size) of 1.1 W/mm/sup 2/ is twice as high as that of the existing over 300 W GaAs-FET amplifiers. A low 5 MHz offset ACLR of -36 dBc with a drain efficiency of 24% is also obtained at 8 dB power back off from the saturated output power.  相似文献   
18.
The objective of this study was to determine the mechanism of a phenomenon peculiar to phase-change recording regarding the mark shape or mark-forming process. The following results were obtained from our simulation of mark shapes, transparency electron microscope observations, and analysis of reproduced signals. A method of calculating a mark shape by calculating the holding-time profile was devised and its appropriateness was confirmed. We found there were close relationships between the cooling pulse shape, the effective erase ratio, the reproduced signal amplitude, and the noise level, and that the temperature change when the mark edge was cooled has a great influence on the stability of the mark shape and crystallized regions  相似文献   
19.
An analysis of a waveguide T junction with an inductive post   总被引:1,自引:0,他引:1  
The authors analyze the T junction with an inductive post, taking its diameter into account for the case where the current distribution is assumed on the surface of the post. A single cylindrical post placed in a T junction improves the impedance matching and compensates the junction discontinuity in a wide frequency band. The effects of the design parameters, such as the diameter of the post and its location, are clarified. The measured return loss is accurately predicted. On the basis of this analysis, an effective design procedure for the T junction is proposed, and the reflection below -30 dB is realized over 4% bandwidth  相似文献   
20.
A 1.3-GHz fifth-generation SPARC64 microprocessor   总被引:1,自引:0,他引:1  
A fifth-generation SPARC64 processor is fabricated in 130-nm partially depleted silicon-on-insulator CMOS with eight layers of Cu metallization. At V/sub dd/ = 1.2 V and T/sub a/ = 25/spl deg/C, it runs at 1.3 GHz and dissipates 34.7 W. The chip contains 191 M transistors with 19 M logic circuits in an area of 18.14 mm /spl times/ 15.99 mm and is covered with 5858 bumps, of which 269 are for I/O signals. It is mounted in a 1360-pin land-grid-array package. The 16-byte-wide system bus operates with a 260-MHz clock in single-data-rate or double-data-rate modes. This processor implements an error-detection mechanism for execution units and data path logic circuits in addition to on-chip arrays to detect data corruption. Intermittent errors detected in execution units and data paths are recovered via instruction retry. A soft barrier clocking scheme allows amortization of the clock skew and jitter over multiple cycles and helps to achieve high clock frequency. Tunability of the clock timing makes timing closure easier. A relatively small amount of custom circuit design and the use of mostly static circuits contributes to achieve short development time.  相似文献   
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