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91.
Methodology for Small-Signal Model Extraction of AlGaN HEMTs 总被引:2,自引:0,他引:2
Both large- and small-periphery AlGaN high- electron mobility transistors (HEMTs) will find applications in microwave systems from 2 to 40 GHz because of their superior power handling capability. A self-consistent approach is presented for the linear model's parameter extraction from measured S-parameters. The model for parasitics is selected to reflect loading from both the probe pads and the interconnect regions, including the air bridges. The objective is to accurately extract intrinsic model parameters as the device periphery is increased from 50 mum to 1 mm and to isolate the effects of device layouts, including air bridging the source regions. To accurately extract the shunt and series parasitics, the device must be represented in its ON- and OFF-states determined by the gate and drain bias. The intrinsic device capacitances are not negligible in the forward and beyond-pinchoff reverse bias states at zero drain bias and must be accounted for. With these corrections to the measured S-parameters, consistent results for the intrinsic device parameters are obtained with both small- and large-periphery AlGaN HEMTs. 相似文献
92.
The effects of exercise, stress and chill temperature on pork muscle characteristics were studied in a 3 × 2 × 2 factorial experiment in which treatments were assigned to blocks made up of six pigs of the same sex from the same litter. Pigs were fed a corn-soybean meal diet with the two littermate pigs on each treatment fed together. Treatments were (1) a control group receiving no exercise and fed in an 8 m(2) pen; (2) a treatment group fed in an 8 m(2) pen and driven 1·6 km/day for 100 days prior to slaughter; and (3) a treatment group fed in pens with 40 m(2) floor space with feeders placed 5 m from their waterers. When the animals averaged approximately 105 kg in weight, one animal from each pair treated alike was subjected to standardized stress. After slaughter, one side was chilled at 2-3°C and the other at 13-15°C for 24 h. Both sides were then chilled at 2-3°C for an additional 24 h. Exercise did not affect average daily gain (ADG), feed efficiency, yield of total wholesale cuts, muscle pH, protein solubility, fiber diameter and sarcomere length of the Longissimus dorsi (LD) and Quadriceps femoris (QF) muscles or the tenderness of the QF muscle. Exercise decreased backfat thickness and the subjective tenderness of the LD muscle. The effects of stress on the characteristics evaluated were consistent with those that have been previously reported. Chilling temperature and interactions involving chilling temperature did not affect any of the characteristics studied. No exercise × stress interactions were observed. Protein solubility values indicated that pale, soft exudative (PSE) muscle was not a factor in any of the treatments. It was concluded that exercise will produce leaner carcasses but less tender muscle and that exercise will not counteract the effects of pre-slaughter stress. 相似文献
93.
Chandna A. Brown R.B. Putti D. Kibler C.D. 《Solid-State Circuits, IEEE Journal of》1995,30(10):1096-1100
This paper describes a new logic style called Power Rail Logic (PRL), which is compatible with direct-coupled FET logic (DCFL) circuits. Multiplexors, latches, flip-flops, and exclusive-OR gates can be built using this logic style. Compared to DCFL, PRL uses fewer transistors, has larger noise margins, and up to 40% lower power-delay products. A test chip containing 32-b barrel shifters designed in DCFL and in PRL was successfully fabricated and tested. Test results are given for both circuits 相似文献
94.
Seoane N. Martinez A. Brown A.R. Barker J.R. Asenov A. 《Electron Devices, IEEE Transactions on》2009,56(7):1388-1395
In this paper, we study the impact of random discrete dopants in the source/drain (S/D) leads on the current variability of a gate-all-around Si nanowire transistor. Due to the strong inhomogeneities of the self-consistent electrostatic potential, a fully 3D real-space nonequilibrium Green's function (NEGF) formalism is used. N-channel transistors with random discrete donors in the S/D regions varying in both numbers and locations have been simulated. We have studied the impact of quasi-bound (QB) states and transmission resonances associated with the attractive potential of the donors on the screening of the impurities and on the current transport. The convergence of the coupled 3D Poisson-NEGF equations for narrow wires with discrete dopants is cumbersome due to the quasi-discrete nature of QB states and resonances of the attractive impurity potential. We present a robust solution strategy dealing with the convergence challenges. Large variations in the on-current and modest variations in the subthreshold slope are observed in the I D-V G characteristics when comparing devices with microscopically different discrete dopant configurations. We have also estimated the access resistance associated with the random dopant regions in the source and the drain leads and find very good agreement with the resistance estimated from the bulk silicon mobility at the same doping concentration. 相似文献
95.
Daniel T. Rooney Louis Gullo Dongji Xie N. Todd Castello Dongkai Shangguan 《Microelectronics Reliability》2007,47(12):2152-2160
This paper presents a study of the optimization of the gold plating thickness for the use of both wire bonding and soldered interconnects on a flexible printed circuit board sample module. Wire bondability is typically better, when the gold plating thickness is greater than 30 μin.; however, the risk of problems with solder joint embrittlement becomes a concern with thick gold plating. In order to better understand the effect of the gold plating thickness on wire bondability and solder joint embrittlement, an evaluation was performed on samples with three ranges of gold plating thicknesses (10–20 μin., 20–30 μin., and 30–45 μin.), on flexible printed circuit board (PCB), substrates. Mechanical shear testing and metallurgical analyses were conducted on chip component solder joints in this three thickness gold study. Thermal shock and drop testing were conducted to evaluate the reliability of the sample modules. Drop testing is especially critical for determining the reliability of the sample modules, which are used in portable consumer electronics products. Reliability testing and metallurgical analyses have been performed to characterize the effect of gold embrittlement on the mechanical integrity of the solder joints with a gold content ranging from 1 to 4 wt.%. 相似文献
96.
The relationship between the elements in the vector of any limit cycle due to rounding in ann-order direct-form digital filter is established. Some bounds on the elements in such vectors are also determined. Sufficient conditions for the accessibility of period-r limit cycles due to rounding inn-order digital filters are presented. 相似文献
97.
The integral equation method of smoothing (IEMS) is applied to the magnetic field integral equation (MFIE) weighted by the exponentialexp (jk_{1}zeta) wherezeta is the stochastic surface height. An integral equation in coordinate space for the average of the product of the surface current and the exponential factor is developed. The exact closed-form solution of this integral equation is obtained based on the specularity of the average scattered field. The complex amplitude of the average scattered field is thus determined by an algebraic equation which clearly shows the effects of multiple scattering on the surface. In addition, it is shown how the incoherent scattered power can be obtained using this method. Comparisons with the Kirchhoff approximation and the dishonest approach are presented, and the first-order smoothing result is shown to be superior to both. 相似文献
98.
Dana Brown John Ferrario Randy Wolf Jing Li Jayendra Bhagat Mustapha Slamani 《Journal of Electronic Testing》2007,23(1):85-94
In this paper, testing of radio frequency (RF) devices with mixed-signal testers is discussed. General purpose automatic test
equipment (ATE) will be used. In this paper, a more universal test structure utilizing RF building blocks is proposed. A global
positioning system (GPS) device is used as an example to illustrate how to develop the RF test plan with this usage. The test
plan developed includes fast, cost-effective and dedicated circuitry.
相似文献
Jing LiEmail: |
99.
Fernando H. garzon Ian D. Raistrick David R. Brown 《Journal of Electronic Materials》1992,21(5):483-485
The continuous monitoring of the conversion, of Y, Cu and BaF2 precursors to form superconductor thin films has been achieved using a fluorine-specific-ion electrode immersed in an effluent
gas-washing cell. High-quality thin films of YBa2Cu3O7-x
deposited on NdGaO3, LaA103 and LaGaO3, have been produced by limiting the wet oxygen annealing phase of the post-deposition anneal. When the films were over-annealed
in humidified oxygen the superconducting transition temperature as measured by inductive methods and the crystal quality,
determined by x-ray rocking curves were degraded. 相似文献
100.
Badeau R.W. Bahar R.I. Bernstein D. Biro L.L. Bowhill W.J. Brown J.F. Case M.A. Castelino R.W. Cooper E.M. Delaney M.A. Deverell D.R. Edmonson J.H. Ellis J.J. Fischer T.C. Fox T.F. Gowan M.K. Gronowski P.E. Herrick W.V. Jain A.K. Meyer J.E. Miner D.G. Partovi H. Peng V. Preston R.P. Somanathan C. Stamm R.L. Thierauf S.C. Uhler G.M. Wade N.D. Wheeler W.R. 《Solid-State Circuits, IEEE Journal of》1992,27(11):1585-1598
A macropipelined CISC microprocessor was implemented in a 0.75-μm CMOS 3.3-V technology. The 1.3-million-transistor custom chip measures 1.62×1.46 cm2 and dissipates 16.3 W. The 100-MHz parts were benchmarked at 50 SPEC marks. The on-chip clocking system and several high-performance logic and circuit techniques are described. Macroinstruction handling, micropipeline management, and control store structures highlight the design architecture. The hierarchical array organization and fast tag comparison technique of the primary cache are discussed. Power estimation procedures are outlined, and the results are compared to measurements. Physical design and verification methods, and CAD tools are also described. After extensive functional verification efforts are described, chip and system test results are presented 相似文献