Channel Modeling and Inter-Carrier Interference Analysis for V2V Communication Systems in Frequency-Dispersive Channels

Vehicle-to-vehicle (V2V) communication has attracted much attention recently. In V2V communications mobility plays a major role in yielding frequency dispersion of the channels, and thus accurately modeling of Doppler effect becomes a challenging issue as the two fundamental assumptions of the Jack’s model may not be valid due to time-varying channel characteristics in V2V communication systems. In this paper, we present a practical model to characterize V2V communication channel and its corresponding Doppler spread spectrum is derived. In addition, we will study the impact of inter-carrier interference (ICI) generated in an orthogonal frequency division multiplexing (OFDM) based V2V communication system. Compared with the classical Jake’s channel model, our proposed new channel model is more accurate and fits in particular well for the performance assessment of vehicle-to-vehicle communication systems.     

Simple and Accurate Design of Low-Density Parity-Check Codes for Multi-Input Multi-Output Systems

In this paper we design an irregular low-density parity-check (LDPC) code for multiple-input multiple-output (MIMO) systems, using a simple extrinsic information transfer (EXIT) chart method. The MIMO systems considered are the optimal maximum a posteriori probability (MAP) detector and the suboptimal minimum mean square error soft-interference cancellation (MMSE-SIC) detector. The MIMO detector and the LDPC decoder exchange soft information and form a turbo iterative receiver. The EXIT charts are used to obtain the edge degree distribution of the irregular LDPC code which is optimized for the MIMO detector. It is shown that the performance of the designed LDPC code is better than that of conventional LDPC code which was optimized for either the Additive White Gaussian Noise (AWGN) channel or the MIMO channel without an explicit consideration of the given detector structure.     

A novel ±0.5 V,high current drive,and rail to rail current operational amplifier

A current operational amplifier (COA) with very high current drive capability is presented in this paper. The principle of operation of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by HSPICE simulation in TSMC 0.18 μm CMOS, BSIM3, and Level49 technology. Owing to the elaborately arranged components, the proposed circuit demonstrates very high frequency bandwidth, extremely high CMRR, high output impedance, and true rail to rail output voltage swing range while operating at very low power supply of ±0.5 V. The interesting results such as current drive capability of ±1 mA, high output impedance of 5 GΩ, wide gain bandwidth of 220 MHz, extremely high output voltage swing of ±0.45 V, which interestingly provides the highest yet reported output voltage compliance for current mode building blocks implemented by regular CMOS technology, low static power consumption of 159 μW, and very high CMRR of 155 dB is achieved utilizing standard CMOS technology. Full process, voltage, and temperature variation analysis of the circuit is also investigated in order to approve the well robustness of the structure. The transient stepwise and sinusoidal response analysis is also done to verify the proposed COA stability.     

Performance Analysis of SEIGA in WCDMA Systems Over Weibull Fading Channels

In this letter, the performance of a Wideband CDMA (W-CDMA) system modeled by a Simplified Expression for Improved Gaussian Approximation (SEIGA), is studied in the presence of a Weibull fading channel. The simulated Bit Error Rate (BER) for W-CDMA systems over Weibull fading channels is computed for the transmission of 10⁶ input bits, and is compared with the corresponding theoretical upper and lower bounds provided by the Q-function. The performance measures are compared for different channel memories.     

Atom Probe Tomography of Zinc Oxide Nanowires

Wide-bandgap zinc oxide (ZnO) semiconductors and nanowires have become important materials for electronic and photonic device applications. In this work, we report the growth of well-aligned single-crystal ZnO nanowire arrays on sapphire substrates by chemical vapor deposition and the development of atom probe tomography, an emerging nanoscale characterization method capable of providing deeper insight into the three-dimensional distribution of atoms and impurities within its structure. Using a metal-catalyst-free approach, the influence of the growth parameters on the orientation and density of the nanowires were studied. The resulting ZnO nanowires were determined to be single crystalline, with diameter on the order of 50 nm to 150 nm and length that could be controlled between 0.5 μm to 20 μm. Their density was on the order of high 10⁸ cm⁻² to low 10⁹ cm⁻². In addition to routine characterizations using scanning and transmission electron microscopy, x-ray diffraction, photoluminescence, and Raman spectroscopy, we developed the atom probe tomography technique for ZnO nanowires, comparing the voltage pulse and laser pulse modes. In-depth analysis of the data was carried out to determine the accurate chemical composition of the nanowires and reveal the incorporation of nitrogen impurities. The current–voltage characteristics of individual nanowires were measured to determine their electrical properties.     

A 1-V, 82-dB, 2.5-MS/s,single loop,single bit delta-sigma modulator in 0.13-μm CMOS technology

It is challenging to design high speed Delta-Sigma modulator using sub-micron process with low supply voltage. Compared with multi-stage or multi-bit design, the single loop, single bit Delta-Sigma modulator has relaxed requirement for the building blocks under low-voltage operation, which make it possible to get high conversion rate by increasing sampling frequency. In this study, a low voltage, high speed 4th-order Delta-Sigma modulator using input feed-forward is presented. Implemented with 0.13-μm CMOS technology and 1.0-V supply voltage, the discrete-time Delta-Sigma modulator achieves 2.5-MS/s conversion rate and 82-dB dynamic range, with the sampling frequency of 160-MHz and OSR of 64.     

A low-voltage low-power threshold voltage monitor for CMOS process sensing

In this paper a low-voltage low-power threshold voltage monitor for CMOS process sensing is presented. This circuit works in weak inversion and it can be used as an elementary circuit block for on-chip compensation of the intra-die or inter-die threshold voltage variations in low-power analog and mixed-signal SoC, since it is robust to temperature and power supply voltage variations (similar to the bandgap voltage reference). The proposed threshold voltage monitor has been successfully verified in a standard 0.35-μm n-well CMOS TSMC process. Experimental results have confirmed that the circuit generates an average reference voltage of 758 mV (very close to the typical threshold voltage when extrapolated to absolute zero) for a 950 mV power supply voltage, with a variation of 39 ppm/°C for the −20 to 80°C temperature range.     

Fast RSVP: Efficient RSVP Mobility Support for Mobile IPv6

In recent years, with the development of mobile communication technologies and the increase of available wireless transmission bandwidth, deploying multimedia services in next generation mobile IPv6 networks has become an inevitable trend. RSVP (resource reservation protocol) proposed by the IETF is designed for hardwired and fixed networks and can not be used in mobile environments. This paper proposes a protocol, called Fast RSVP, to reserve resources for mobile IPv6. The protocol adopts a cross-layer design approach where two modules (RSVP module and Mobile IPv6 module) at different layers cooperate with each other. Fast RSVP divides a handover process with QoS guarantees into two stages: (1) setup of the resource reservation neighbor tunnel and (2) resource reservation on the optimized route. It can help a mobile node realize fast handover with QoS guarantees as well as avoid resource wasting by triangular routes, advanced reservations and duplicate reservations. In addition, fast RSVP reserves “guard channels” for handover sessions, thus greatly reducing the handover session forced termination rate while maintaining high performance of the network. Based on extensive performance analysis and simulations, Fast RSVP, compared with existing methods of resource reservation in mobile environments, performs better in terms of packet delay and throughput during handover, QoS recovery time after handover, resource reservation cost, handover session forced termination rate and overall session completion rate.     

Cu Substrates with Different Grain Sizes

Cu₆Sn₅ and Cu₃Sn are easily formed at the interface between Sn and Cu during reflow and aging processes. Thick Cu-Sn compounds at the interface become brittle, reducing the mechanical strength of solder joints and increasing the consumption of under bump metallization (UBM). It is noted that intermetallic compound (IMC) growth and substrate consumption are affected by factors such as substrate fabrication, substrate orientation, and substrate microstructure. In this study, to determine the effects of substrate grain size on IMC growth and substrate consumption, pure Sn solder was reflowed on annealed Cu substrates with different grain sizes at 250°C for 30 s to 600 s. It was revealed that Cu substrates with smaller grain sizes exhibited reduced IMC growth. In addition, the interdiffusion coefficients of Cu₆Sn₅ and Cu₃Sn were decreased for the Cu substrate with the smaller grain size. The influence of the Cu substrate grain size on IMC growth and substrate consumption is discussed.     

Topological Patterns for Scalable Representation and Analysis of Dataflow Graphs

Tools for designing signal processing systems with their semantic foundation in dataflow modeling often use high-level graphical user interfaces (GUIs) or text based languages that allow specifying applications as directed graphs. Such graphical representations serve as an initial reference point for further analysis and optimizations that lead to platform-specific implementations. For large-scale applications, the underlying graphs often consist of smaller substructures that repeat multiple times. To enable more concise representation and direct analysis of such substructures in the context of high level DSP specification languages and design tools, we develop the modeling concept of topological patterns, and propose ways for supporting this concept in a high-level language. We augment the dataflow interchange format (DIF) language—a language for specifying DSP-oriented dataflow graphs—with constructs for supporting topological patterns, and we show how topological patterns can be effective in various aspects of embedded signal processing design flows using specific application examples.