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We present a circuit-level technique of designing a lower write-power along with variability-resistant 9-MOFTET static random-access memory cell. Our proposed bitcell exhibits lower write-power consumption owing to reduction of activity factor and breakup of feedback path between the cross-coupled inverters during write operation. It exhibits higher read static noise margin (by 3.09 ×) compared with standard 6T SRAM cell @ minimum-area. LP9T shows higher static margin for write operation (by 41%) compared with 8T (S6T) @ iso-area (minimum-area). These improvements are achieved due to breakup of feedback path during the process of writing a bit on to the storage node. The paper investigates in detail the influence of variation in process related parameters, environmental parameters such as supply voltage and temperature on most of the important design parameters of the bitcell and compares the obtained simulation results with conventional 6-MOSFET (6T) and 8-MOSFET (8T) bitcells. It demonstrates its invariableness by showing 1.5 × tighter disperse in read time variability with a cost of 1.41 × higher read time compared with S6T @ minimum-area. It also exhibits 39% narrower disperse in read time variability in comparison to 8T @ iso-area. It draws lower power (2.06 ×) from supply voltage while flipping of stored data during write mode compared with standard 8T SRAM cell @ iso-area. It also compares key design metrics of LP9T with those of few other 9T SRAM cells found in the literature. This work also realizes the proposed design using CNFET. The CNFET-based design outperforms its CMOS counterpart in all respect.
相似文献In this paper a 2.4-GHz non-return to zero (abbreviated as NRZ) active downconversion mixer for transceiver system is demonstrated. It features with the double- balanced topology, NRZ mechanism, an effecting biasing technique and a current mirror technique are used to achieve the requirements. Downconversion mixer is realized on 180 nm CMOS technology. Despite of trade-off between conversion gain and linearity we can achieve very high conversion gain with moderate linearity. Simulations using cadence tool exhibits a conversion gain of 24.61 dB, a third order intercept point of 6.17 dB, a 1-dB compression point of − 5.86 dB and a second order intercept point of + 87.66 dB at 1.8 V supply.
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