Learning Photometric Invariance for Object Detection

Color is a powerful visual cue in many computer vision applications such as image segmentation and object recognition. However, most of the existing color models depend on the imaging conditions that negatively affect the performance of the task at hand. Often, a reflection model (e.g., Lambertian or dichromatic reflectance) is used to derive color invariant models. However, this approach may be too restricted to model real-world scenes in which different reflectance mechanisms can hold simultaneously.     

Guaranteed cost control analysis and iterative design for constrained Takagi–Sugeno systems

This paper presents a novel control design technique in order to obtain a guaranteed cost fuzzy controller subject to constraints on the input channel. This guaranteed cost control law is obtained via multi-parametric quadratic programming. The result is a piecewise fuzzy control law where the state partition is defined by fuzzy inequalities. The parameters of the Lyapunov function can be obtained previously using Linear Matrix Inequalities optimization.     

Information systems in the public sector: The e-Government enactment framework

Despite the burgeoning number of studies of public sector information systems, very few scholars have focussed on the relationship between e-Government policies and information systems choice and design. Drawing on Fountain’s (2001) technology enactment framework, this paper endeavours to conduct an in-depth investigation of the intricacies characterising the choice and design of new technologies in the context of e-Government reforms. By claiming that technologies are carriers of e-Government reform aims, this study investigates the logics embedded in the design of new technology and extant political interests and values inscribed in e-Government policies. The e-Government enactment framework is proposed as a theoretical and analytical approach to understand and study the complexity of these relationships which shape e-Government policies.     

A CSP model for simple non-reversible and parallel repair plans

This work presents a constraint satisfaction problem (CSP) model for the planning and scheduling of disassembly and assembly tasks when repairing or substituting faulty parts. The problem involves not only the ordering of assembly and disassembly tasks, but also the selection of them from a set of alternatives. The goal of the plan is the minimization of the total repairing time, and the model considers, apart from the durations and resources used for the assembly and disassembly tasks, the necessary delays due to the change of configuration in the machines, and to the transportation of intermediate subassemblies between different machines. The problem considers that sub-assemblies that do not contain the faulty part are nor further disassembled, but allows non-reversible and parallel repair plans. The set of all feasible repair plans are represented by an extended And/Or graph. This extended representation embodies all of the constraints of the problem, such as temporal and resource constraints and those related to the selection of tasks for obtaining a correct plan.     

The joint Gateway Placement and Spatial Reuse Problem in Wireless Mesh Networks

A Wireless Mesh Network (WMN) is composed of multiple Access Points (APs) that are connected together using the radio channel and by a limited number of gateway APs connected to the Internet. In this paper, we address the problem of gateway placement that consists of minimizing the number of gateways while satisfying system performance requirements. Along with the placement problem, the formulation includes joint routing and scheduling to account for the problem of interference and to enable spacial reuse. The problem, which we coined GPSRP (Gateway Placement and Spatial Reuse Problem), allows a much more efficient use of the available resources and reduces overall gateway costs. This article presents for the first time a mathematical formulation of the problem and discusses its advantages and limitations with respect to other approaches.     

Network interfaces for programmable NICs and multicore platforms

The availability of multicore processors and programmable NICs, such as TOEs (TCP/IP Offloading Engines), provides new opportunities for designing efficient network interfaces to cope with the gap between the improvement rates of link bandwidths and microprocessor performance. This gap poses important challenges related with the high computational requirements associated to the traffic volumes and wider functionality that the network interface has to support. This way, taking into account the rate of link bandwidth improvement and the ever changing and increasing application demands, efficient network interface architectures require scalability and flexibility. An opportunity to reach these goals comes from the exploitation of the parallelism in the communication path by distributing the protocol processing work across processors which are available in the computer, i.e. multicore microprocessors and programmable NICs.Thus, after a brief review of the different solutions that have been previously proposed for speeding up network interfaces, this paper analyzes the onloading and offloading alternatives. Both strategies try to release host CPU cycles by taking advantage of the communication workload execution in other processors present in the node. Nevertheless, whereas onloading uses another general-purpose processor, either included in a chip multiprocessor (CMP) or in a symmetric multiprocessor (SMP), offloading takes advantage of processors in programmable network interface cards (NICs). From our experiments, implemented by using a full-system simulator, we provide a fair and more complete comparison between onloading and offloading. Thus, it is shown that the relative improvement on peak throughput offered by offloading and onloading depends on the rate of application workload to communication overhead, the message sizes, and on the characteristics of the system architecture, more specifically the bandwidth of the buses and the way the NIC is connected to the system processor and memory. In our implementations, offloading provides lower latencies than onloading, although the CPU utilization and interrupts are lower for onloading. Taking into account the conclusions of our experimental results, we propose a hybrid network interface that can take advantage of both, programmable NICs and multicore processors.     

Aligned texture map creation for pose invariant face recognition

In last years, Face recognition based on 3D techniques is an emergent technology which has demonstrated better results than conventional 2D approaches. Using texture (180° multi-view image) and depth maps is supposed to increase the robustness towards the two main challenges in Face Recognition: Pose and illumination. Nevertheless, 3D data should be acquired under highly controlled conditions and in most cases depends on the collaboration of the subject to be recognized. Thus, in applications such as surveillance or control access points, this kind of 3D data may not be available during the recognition process. This leads to a new paradigm using some mixed 2D-3D face recognition systems where 3D data is used in the training but either 2D or 3D information can be used in the recognition depending on the scenario. Following this concept, where only part of the information (partial concept) is used in the recognition, a novel method is presented in this work. This has been called Partial Principal Component Analysis (P²CA) since they fuse the Partial concept with the fundamentals of the well known PCA algorithm. This strategy has been proven to be very robust in pose variation scenarios showing that the 3D training process retains all the spatial information of the face while the 2D picture effectively recovers the face information from the available data. Furthermore, in this work, a novel approach for the automatic creation of 180° aligned cylindrical projected face images using nine different views is presented. These face images are created by using a cylindrical approximation for the real object surface. The alignment is done by applying first a global 2D affine transformation of the image, and afterward a local transformation of the desired face features using a triangle mesh. This local alignment allows a closer look to the feature properties and not the differences. Finally, these aligned face images are used for training a pose invariant face recognition approach (P²CA).     

Exploiting address compression and heterogeneous interconnects for efficient message management in tiled CMPs

High performance processor designs have evolved toward architectures that integrate multiple processing cores on the same chip. As the number of cores inside a Chip MultiProcessor (CMP) increases, the interconnection network will have significant impact on both overall performance and energy consumption as previous studies have shown. Moreover, wires used in such interconnect can be designed with varying latency, bandwidth and power characteristics. In this work, we show how messages can be efficiently managed in tiled CMP, from the point of view of both performance and energy, by combining both address compression with a heterogeneous interconnect. In particular, our proposal is based on applying an address compression scheme that dynamically compresses the addresses within coherence messages allowing for a significant area slack. The arising area is exploited for wire latency improvement by using a heterogeneous interconnection network comprised of a small set of very-low-latency wires for critical short-messages in addition to baseline wires. Detailed simulations of a 16-core CMP show that our proposal obtains average improvements of 10% in execution time and 38% in the energy-delay² product of the interconnect. Additionally, the sensitivity analysis shows that our proposal performs well when either OoO cores or caches with higher latencies are considered.     

Liquid recirculation in microfluidic channels by the interplay of capillary and centrifugal forces

We demonstrate a technique to recirculate liquids in a microfluidic channel by alternating predominance of centrifugal and capillary forces to rapidly bring the entire volume of a liquid sample to within one diffusion length, δ, of the surface, even for sample volumes hundreds of times the product of δ and the geometric device area. This is accomplished by repetitive, random sampling of an on-disc sample reservoir to form a thin fluid layer of thickness δ in a microchannel, maintaining contact for the diffusion time, then rapidly exchanging the fluid layer for a fresh aliquot by disc rotation and stoppage. With this technique, liquid volumes of microlitres to millilitres can be handled in many sizes of microfluidic channels, provided the channel wall with greatest surface area is hydrophilic. We present a theoretical model describing the balance of centrifugal and capillary forces in the device and validate the model experimentally.