Hydrodynamics and heat transfer characteristics of passive decay heat removal systems: CFD simulations and experimental measurements

In nuclear safety operations, condensing heat transfer area is placed in a large pool of liquid to accommodate passive thermal decay. Such systems are subject to pool boiling and thermal stratification. Velocity and temperature measurements were carried out in a 300 mm i.d. vessel with a central tube as the heat transfer area. For this purpose, particle image velocimetry (PIV) and hot film anemometry (HFA) were employed. Further, CFD simulations of this system were performed. An excellent agreement was found between the experimental measurements and the CFD simulations. For modeling, the boiling was an extension of the model of Krepper et al. (2007). The lift force was described according to the recommendations of Zeng et al. (1993). The stratification occurring inside the pool has been quantified in terms of a dimensionless number (stratification number). It has been observed that, for higher heat input rates stratification occurs in a shorter time period. The effect of submergence of the condenser tube in the large pool has been studied and it has been found that, for any height of submergence, vapors form at the top of the pool but placing the condenser near the bottom may reduce stratification to a certain extent. The model was extended to the real size (50 000 mm I.D.) passive decay heat removal system.     

Functional Properties of Soy Protein Isolates Produced from Ultrasonicated Defatted Soy Flakes

This study aimed to determine the effect of pretreating defatted soy flakes with ultrasound on soy protein isolate (SPI) yield and functionality. Defatted soy flakes dispersed into water (16%, w/w) were sonicated for 30, 60 and 120 s at ultrasonic amplitudes of 21 and 84 μm_pp (peak to peak amplitude in μm), representing low and high power, respectively. The power densities were 0.30 and 2.56 W mL⁻¹, respectively. The SPI yield increased by 13 and 34%, after sonication for 120 s at low and high power, respectively. The sonication of defatted soy flakes for 120 s at the higher power level improved the SPI solubility by 34% at pH 7.0, while decreasing emulsification and foaming capacities by 12 and 26%, respectively, when compared to control SPI. Rheological behavior of the SPI was also modified with significant loss in consistency coefficient due to sonication. Some of these results could be explained by the loss of the protein native state with increased sonication time and power.     

Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique

With increasing defect density and process variations in nanometer technologies, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. This paper presents a novel test technique based on supply gating, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overhead. Experimental results on a set of ISCAS89 benchmarks show an average reduction of 34% in area overhead with an average improvement of 65% in delay overhead and 90% in power overhead during normal mode of operation, compared to the enhanced scan implementation.

Determination of worker physiological cost in workspace reach envelopes

Oxygen uptake (VO2), heart rate (HR) and myoelectric activity (EMG) were measured while performing a repetitive task in the normal, maximum and extreme workspace reach envelopes. The VO2 and HR increased significantly from the normal to the maximum to the extreme workspace reach envelope. The average increases in VO2 when compared to the normal workspace were 19 and 52%, respectively. The corresponding average increases in HR were 6 and 14%, respectively. The increase in EMG for anterior deltoid, upper trapezious and erector spinae showed a significant increase from normal to maximum and from maximum to extreme workspaces. The average increases in EMG for anterior deltoid, upper trapezious and erector spinae, compared to the normal workspace were 96, 37 and 48% respectively for the maximum workspace and 193, 95 and 106% for the extreme workspace, respectively. The research indicated for the first time that during task performance, worker physiological cost would increase significantly with the increase in workspace reach levels.     

A Robust Fingerprint Indexing Scheme Using Minutia Neighborhood Structure and Low-Order Delaunay Triangles

Fingerprint indexing is a key technique in automatic fingerprint identification systems (AFIS). However, handling fingerprint distortion is still a problem. This paper concentrates on a more accurate fingerprint indexing algorithm that efficiently retrieves the top N possible matching candidates from a huge database. To this end, we design a novel feature based on minutia neighborhood structure (we call this minutia detail and it contains richer minutia information) and a more stable triangulation algorithm (low-order Delaunay triangles, consisting of order 0 and 1 Delaunay triangles), which are both insensitive to fingerprint distortion. The indexing features include minutia detail and attributes of low-order Delaunay triangle (its handedness, angles, maximum edge, and related angles between orientation field and edges). Experiments on databases FVC2002 and FVC2004 show that the proposed algorithm considerably narrows down the search space in fingerprint databases and is stable for various fingerprints. We also compared it with other indexing approaches, and the results show our algorithm has better performance, especially on fingerprints with distortion.     

Experimental investigation on the impact of stress free temperature on the electromigration performance of copper dual damascene submicron interconnect

Electromigration experiments are conducted for submicron dual damascene copper lower level interconnect samples of different stress free temperatures. The electromigration life-time is found to be strongly depend on the stress state of the metallization and the stress gradient that exist due to thermal mismatch of various materials surrounding the copper metallization. It is found that by reducing the stress free temperature, electromigration lifetime can be improved. In order to explain the life-time behavior, an atomic flux divergence based coupled field finite element model is developed. The model predicts a reduction in the atomic flux divergence at the electromigration test condition due to the reduction in the stress free temperature as the key factor responsible for longer electromigration life-time observed experimentally.     

Building contextual classifiers by integrating fuzzy rule based classification technique and k-nn method for credit scoring

Credit-risk evaluation is a very challenging and important problem in the domain of financial analysis. Many classification methods have been proposed in the literature to tackle this problem. Statistical and neural network based approaches are among the most popular paradigms. However, most of these methods produce so-called “hard” classifiers, those generate decisions without any accompanying confidence measure. In contrast, “soft” classifiers, such as those designed using fuzzy set theoretic approach; produce a measure of support for the decision (and also alternative decisions) that provides the analyst with greater insight. In this paper, we propose a method of building credit-scoring models using fuzzy rule based classifiers. First, the rule base is learned from the training data using a SOM based method. Then the fuzzy k-nn rule is incorporated with it to design a contextual classifier that integrates the context information from the training set for more robust and qualitatively better classification. Further, a method of seamlessly integrating business constraints into the model is also demonstrated.     

Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current

In recent years, Defect Oriented Testing (DOT) has been investigated as an alternative testing method for analog circuits. In this paper, we propose a wavelet transform based dynamic supply current (IDD) analysis technique for detecting catastrophic and parametric faults in analog circuits. Wavelet transform has the property of resolving events in both time and frequency domain simultaneously unlike Fourier transform which decomposes a signal in frequency components only. Simulation results on benchmark circuits show that wavelet transform has higher fault detection sensitivity than Fourier or time-domain methods and hence, can be considered very promising for defect oriented testing of analog circuits. Effectiveness of wavelet transform based DOT amidst process variation and measurement noise is studied.This research is supported in part by MARCO GSRC under contract number SA3273JB.A paper based on this work was presented at the Fourth IEEE Latin American Test Workshop, Natal, Brazil, February 2003.Swarup Bhunia received the undergraduate degree from Jadavpur University, Calcutta, India, and the Masters degree from the Indian Institute of Technology (IIT), Kharagpur. He is currently working toward the Ph.D. degree in the Department of Electrical Engineering, Purdue University, West Lafayette, IN.He has worked in the EDA industry on RTL synthesis and verification since 2000. His research interest includes defect-based testing, diagnosis, noise analysis, and noise-aware design.Arijit Raychowdhury received the B.E. degree in 2001 in electronics and telecommunication engineering from Jadavpur University, India. He is currently pursuing the Ph.D. degree in electrical and computer engineering in Purdue University, West Lafayette, IN.He has worked as an analog circuit designer in Texas Instruments India. His research interests include device/circuit design for scaled silicon and nonsilicon devices. He has received academic excellence awards in 1997, 2000, and 2001 and Messner Fellowship from Purdue University in 2002. Mr. Raychowdhury has been awarded the Best Student Paper Award in the IEEE Nanotechnology Conference, 2003.Kaushik Roy received the B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and the Ph.D. degree from the Electrical and Computer Engineering Department, University of Illinois, Urbana, in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, TX, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty, Purdue University, West Lafayette, IN, in 1993, where he is currently a Professor. His research interests include VLSI design/CAD with particular emphasis in low-power electronics for portable computing and wireless communications, VLSI testing and verification, and reconfigurable computing. He has published more than 250 papers in refereed journals and conferences, holds six patents, and is Co-Author of a book on Low Power CMOS VLSI Design (New York: Wiley). He was Guest Editor for a Special Issue on Low-Power VLSI in IEE Proceedings—Computers and Digital Techniques (July 2002). Dr. Roy received the National Science Foundation Career Development Award in 1995, the IBM Faculty Partnership Award, AT&T/Lucent Foundation Award, Best Paper Awards at the 1997 International Test Conference and 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, and 2003 IEEE Nano. He is on the Editorial Board of IEEE Design and Test, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, and IEEE TRANSACTIONS ON VLSI SYSTEMS. He was Guest Editor for a Special Issue on Low-Power VLSI in IEEE DESIGN AND TEST (1994), and for the IEEE TRANSACTIONS ON VLSI SYSTEMS (June 2000).