Current-mode full-duplex (CMFD) signaling for high-speed chip-to-chip interconnect

In this work we propose a new current-mode full-duplex (CMFD) signaling scheme for high-speed chip-to-chip data communication. In this scheme, all the internal nodes of the link are maintained at low-impedance, facilitating high-speed data communication. A new hybrid circuit topology required for separating the inbound signal from the outbound signal is presented. The proposed current-mode hybrid is realized by a source-coupled main driver, a scaled down replica stage and a common-gate (CG) transimpedance amplifier (TIA). Detailed design, analysis, noise and jitter characterization of the proposed hybrid is presented. The hybrid is realized in 1.8 V, digital CMOS technology. Using this hybrid circuit topology, CMFD signaling over a chip-to-chip interconnect is demonstrated. The post-layout performance shows 8 Gb/s data transfer rate over a FR4 PCB trace of length 7.5 in. for a target bit-error rate (BER) of 10⁻¹². The FR4 PCB trace is modeled by measured 4-port S-parameters in the frequency range from 100 MHz to 20 GHz. The input-referred noise current of the receiver and output-noise voltage of transmitter are and 5.34 mV, respectively. The standalone power consumption of the hybrid is 14.64 mW.     

Characteristics of a variable length ring oscillator and its use in PLL based systems

This paper describes the properties of a multiplexer based variable length ring oscillator and the effects of using it as a voltage controlled oscillator (VCO) in a phase locked loop (PLL) based system. The application of the proposed VCO in a PLL used as an FM demodulator or as a frequency synthesizer has been examined and it has been shown that the length control facility of the VCO could be used for improving the performances of those systems. Hardware experimental results confirm the predictions regarding the performance enhancement.     

Wavelet-based image coding using nonlinear interpolative vectorquantization

We propose a reduced complexity wavelet-based image coding technique. Here, 64-D (for three stages of decomposition) vectors are formed by combining appropriate coefficients from the wavelet subimages, 16-D feature vectors are then extracted from the 64-D vectors on which vector quantization (VQ) is performed. At the decoder, 64-D vectors are reconstructed using a nonlinear interpolative technique. The proposed technique has a reduced complexity and has the potential to provide a superior coding performance when the codebook is generated using the training vectors drawn from similar images.     

An automated high-level topology generation procedure for continuous-time ΣΔ modulator

This paper presents an automated procedure for generation of high-level topologies for continuous-time ΣΔ modulator system. A functional topology of the system is generated from the given transfer function model of the modulator. Mathematical transformation technique is applied iteratively over the initial topology to generate a functional topology which is optimized for modulator sensitivity, hardware complexity and relative power consumption. This is then implemented using behavioral models of operational transconductance amplifiers and capacitors. The generated high-level topology is ensured to work with reasonable accuracy under non-ideal conditions. The entire procedure has been implemented in Matlab/Simulink environment. Numerical results have been provided to demonstrate the procedure.     

Intercarrier bandwidth exchange: an engineering framework

A mismatch between demand and supply for bandwidth is common in transport carrier networks. This mismatch is generally a result of the disparity between a carrier's capacity buildout and its anticipated customer demand. A carrier with temporary bandwidth deficit or lack of presence in a geographical region and a carrier with surplus capacity in the right locations can be brought together by the emerging bandwidth exchange technology. Bandwidth exchange offers a win-win solution, in which the carrier with a deficit avoids losing revenue by buying capacity from the carrier with surplus, and the latter makes additional revenue by retail sale of its excess capacity. While the concept of real-time purchase and exchange of bandwidth has attracted a lot of attention, many technical challenges stand in the way of making it a reality. The purpose of this article is to provide an engineering framework for enabling real-time bandwidth exchange with committed quality of service and service level agreement among transport carriers. Special emphasis is given to identifying the architectural requirements and the enabling infrastructure necessary for building a viable bandwidth exchange that can be used for creating revenue out of surplus stranded capacity. Indepth analysis of cross-carrier service level agreement specification, capacity publication, route design, and service provisioning are also provided in the article.     

Half-Rate Duobinary Transmitter Architecture for Chip-to-Chip Interconnect Applications

For a high speed duobinary transmitter clock frequency defines the transmission limit. A conventional duobinary transmitter needs a clock frequency equal to the data rate. In this work we propose a duobinary transmitter that uses a clock frequency half of the output data rate and hence achieves double the transmission rate for a given clock frequency as compared to a conventional duobinary transmitter. In the proposed transmitter the duobinary precoder is integrated into the last stage of a tree structured serializer to combine two NRZ data streams at half the transmission data rate. Two modes for the precoder have been incorporated into the design. The first mode is applicable for data transmission over copper whereas the second mode is suitable for wavelength division multiplexed optical transmission. A DLL based clock multiplier unit is employed to produce the high frequency clock with 50% duty cycle needed for the precoding operation. It incorporates a clock generation logic with integrated duty cycle control. A charge pump with dynamic current matching and a high resolution PFD are employed to reduce static phase error in locking and hence achieves improved jitter performance. A new delay cell along with automatic mode selection is proposed. To cover a wide range of data rate, the DLL is designed for a wide locking range and maintains almost 50% duty cycle. The design is implemented in 1.8-V, 0.18 μm Digital CMOS technology with an f _T of 27 GHz. Simulations shows that, the duobinary transmitter circuit works up-to 10 Gb/s and consumes 60 mW of power.     

<Emphasis Type="Italic">Ab Initio</Emphasis> Studies of Hydrogen Defects in CdTe

Using first-principles calculations based on density functional theory, we have investigated the nature of H defects in CdTe. The formation energy calculations indicate that the ground state position of the H inside the CdTe lattice depends on charge state: the lowest energy position for H⁰ and H⁺ is at the bond center site, while H⁻ prefers the tetrahedral interstitial site with Cd nearest neighbors (T_Cd). We find that H in CdTe acts as an amphoteric impurity. In p-type samples, H is in a positive charge state, acting as a donor to neutralize the free holes in the valence band, and in n-type samples H acquires an electron, compensating the donors in the sample.     

Three-dimensional finite element analysis to predict the effects of SAW process parameters on temperature distribution and angular distortions in single-pass butt joints with top and bottom reinforcements

Achieving adequate top and bottom reinforcement is important to minimize angular distortions in single-pass submerged arc welded (SAW) butt joints. This is achieved in the present work by using a reusable flux-filled backing strip and proper SAW process parameters without resorting to costly distortion mitigation techniques. The butt joints were made without edge (square butts) preparation. The process was also modeled by using three-dimensional finite element analysis by incorporating the top and bottom reinforcements into the modeling. Filler material deposition was also simulated. Temperature distributions and angular distortions obtained from the modeling closely matched with the experimental values. Thus, the cost effective experimental methodology established in the present work can be utilized for minimizing angular distortions in SAW square butts. The modeling methodology adopted can be used for predicting the angular distortions in SAW square butts with top and bottom reinforcements.     

Dynamic Effect of Soil-Tunnel Interface Under Dynamic Loading

Soil Mechanics and Foundation Engineering - The resilience of the Daikai subway station during the Kobe earthquake is taken as a case study of tunnel endurance at various points under different...     

Interpenetrating polymer networks of photocrosslinkable cellulose derivatives

A series of interpenetrating polymer networks has been prepared from two cellulose derivatives, one of which contains cinnamate groups and the other containing randomly substituted cinnamate and allyl groups. The latter derivative forms a crosslinked network in less than 5 min on exposure to ultraviolet radiation and can be used to make amorphous interpenetrating polymer networks containing 50% by weight loading level of crosslinked vinyl polymers. The syntheses of both derivatives and the thermal properties and film morphologies of their interpenetrating polymer networks are discussed. © 1996 John Wiley & Sons, Inc.