Exposed Die-Top Encapsulation Molding for an Improved High- Performance Flip Chip BGA Package

The recent advancement in high- performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip ball grid array (BGA) package with high pin count and targeted reliability has emerged as a popular choice. The flip chip technology can accommodate an I/O count of more than five hundreds500, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. None the less, greater expectations on these high-performance packages arose such as better substrate real estate utilization for multiple chips, ease in handling for thinner core substrates, and improved board- level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planar top surface can be formed. A, and a flat lid can then be mounted on the planar mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multichip package and thin core substrate options. Finite-element simulations have been employed for the study of its structural integrity, thermal, and electrical performances. Detailed package and board-level reliability test results will also be reported     

Routing Correlated Data with Fusion Cost in Wireless Sensor Networks

In this paper, we propose a routing algorithm called minimum fusion Steiner tree (MFST) for energy efficient data gathering with aggregation (fusion) in wireless sensor networks. Different from existing schemes, MFST not only optimizes over the data transmission cost, but also incorporates the cost for data fusion, which can be significant for emerging sensor networks with vectorial data and/or security requirements. By employing a randomized algorithm that allows fusion points to be chosen according to the nodes' data amounts, MFST achieves an approximation ratio of 5/4log(k + 1), where k denotes the number of source nodes, to the optimal solution for extremely general system setups, provided that fusion cost and data aggregation are nondecreasing against the total input data. Consequently, in contrast to algorithms that only excel in full or nonaggregation scenarios without considering fusion cost, MFST can thrive in a wide range of applications     

Progressive damage modelling of SMC composite materials

The present work deals with the modelling of damage behaviour for sheet moulding compound (SMC) composite materials using a finite element analysis package. Specifically, a comparison is made between the results obtained experimentally for a three-point bending test, and those obtained from numerical simulation using a material model already implemented. The simulation has been performed for the material models available within the PAM-CRASH software. The simulation results are compared and validated with respect to experimentation.     

Nanoscale Crystallization in Amorphous Fe–P–Mn Alloys

Mössbauer effect measurements and physicochemical analysis demonstrate that annealing of amorphous Fe–P–Mn alloys leads to the formation of a nanocrystalline structure.     

TEM Studies of High Temperature Corrosion Behaviour of TiAl Intermetallics with Surface Modifications

The oxidation/sulphidation behaviour of a Ti‐46.7Al‐1.9W‐0.5Si alloy with a TiAl₃ diffusion coating was studied in an environment of H₂/H₂S/H₂O at 850^oC. The kinetic results demonstrate that the TiAl₃ coating significantly increased the high temperature corrosion resistance of Ti‐46.7Al‐1.9W‐0.5Si. The SEM, EDX, XRD and TEM analysis reveals that the formation of an Al₂O₃ scale on the surface of the TiAl₃‐coated sample was responsible for the enhancement of the corroison resistance. The Ti‐46.7Al‐1.9W‐0.5Si alloy was also modified by Nb ion implantation. The Nb ion implanted and as received sampels were subjected to cyclic oxidation in an open air at 800^oC. The Nb ion implantation not only increased the oxidation resistance but also substantially improved the adhesion of scale to the substrate.     

Graph-theoretic construction of low-density parity-check codes

This article presents a graph-theoretic method for constructing low-density parity-check (LDPC) codes from connected graphs without the requirement of large girth. This method is based on finding a set of paths in a connected graph, which satisfies the constraint that any two paths in the set are either disjoint or cross each other at one and only one vertex. Two trellis-based algorithms for finding these paths are devised. Good LDPC codes of practical lengths are constructed and they perform well with iterative decoding.     

Extracting Light from Polymer Light‐Emitting Diodes Using Stamped Bragg Gratings

In this paper, we describe a method for increasing the external efficiency of polymer light‐emitting diodes (LEDs) by coupling out waveguided light with Bragg gratings. We numerically model the waveguide modes in a typical LED structure and demonstrate how optimizing layer thicknesses and reducing waveguide absorption can enhance the grating outcoupling. The gratings were created by a soft‐lithography technique that minimizes changes to the conventional LED structure. Using one‐dimensional and two‐dimensional gratings, we were able to increase the forward‐directed emission by 47 % and 70 %, respectively, and the external quantum efficiency by 15 % and 25 %.     

Reliability studies of MOCVD TiSiN and EnCoRe Ta(N)/Ta

Passivated single damascene copper SiO₂ damascene lines were evaluated in combination with TiSiN and Ta(N)/Ta diffusion barriers. Leakage current, breakdown and time-dependent dielectric breakdown properties were investigated on a wafer level basis for temperatures ranging between room temperature and 150 °C. It is found that the leakage performance of the wafers with a TiSiN barrier is better at room temperature, but at 150 °C the performance levels out with Ta(N)/Ta. Time-dependent dielectric breakdown measurements at 150 °C show that the lifetime of the interconnect is higher with the selected Ta(N)/Ta barrier than for TiSiN.