涡轮搅拌桨反应器混合过程的数值计算

利用CFD方法计算单层涡轮反应器搅拌槽内流体混合过程的速度场和浓度场,研究物料在搅拌槽内的混合过程,以及不同监测点对混合时间的影响。结果表明,搅拌槽内物料的混合主要受槽内流体的流动形式所影响;混合时间的长短与监测点位置有关;在搅拌桨的桨叶附近进行监测所得到的混合时间较短,在液面附近进行监测所得的混合时间较长。在实际生产和试验中,应注意对监测点位置的选取。     

降低成品油二次物流运输成本的思考

介绍了传统成品油进货和管理模式存在的诸如成品油物流以行政区划、中问环节多、信息化程度不高、运输路线未优化造成物流成本提高等问题。提出要降低成品油二次物流运输成本，当务之急是加强成品油物流的信息化建设；调整管理模式，打破行政区域界限，开展经济辐射半径内的库站物流配送；引进竞争机制，打破运输垄断，一、二次物流结合，大、小车型搭配，提高运营效率；做好运杂费全面预算、核算及运行费用的过程控制。     

丙烯腈装置回收塔内聚合物生成原因的分析

针对丙烯腈生产过程中回收塔内聚合物堵塞降液管造成回收塔运行周期短的问题,通过对丙烯腈回收塔内各组分分布的模拟计算,直观显示了回收塔内各组分的浓度分布,发现了回收塔的聚合段与丙烯醛的富集段相吻合的现象,初步得出了回收塔内局部聚合的原因;通过对塔内聚合物的特性分析和评判,进一步证实了“回收塔内局部聚合严重是由于在聚合段丙烯醛聚集引起”这一现象;根据模拟计算结果和实际运行经验,提出了预防聚合物堵塞降液管的措施,并进行了部分生产验证,为丙烯腈生产企业延长装置运行周期提供了理论指导。     

Reducing CIC filter complexity

This paper provides several tricks to reduce the complexity and enhance the usefulness of cascaded integrator-comb (CIC) filters. The first trick shows a way to reduce the number of adders and delay elements in a multi-stage CIC interpolation filter. The result is a multiplierless scheme that performs high-order linear interpolation using CIC filters. The second trick shows a way to eliminate the integrators from CIC decimation filters. The benefit is the elimination of unpleasant data word growth problems.     

Degree-of-polarization and eye-closure penalty associated with optical signals with orthogonal polarizations

We perform a systematic measurement of the degree-of-polarization (DOP) and eye-closure penalty for optical signals with orthogonal polarizations. We find that the symmetry of DOP is maintained for the orthogonal polarizations under both first and higher order polarization-mode dispersion (PMD), whereas the symmetry of eye-closure penalty is broken under second-order PMD. An orthogonal polarization pair can have large disparity of eye-closure penalty despite an identical DOP. We also demonstrate a novel approach to estimate the maximum eye-closure penalty asymmetry with three orthogonal polarizations on the Poincare/spl acute/ sphere.     

Unified Systolic-Like Architecture for DCT and DST Using Distributed Arithmetic

A common computing-core representation of the discrete cosine transform and discrete sine transform is derived and a reduced-complexity algorithm is developed for computation of the proposed computing-core. A parallel architecture based on the principle of distributed arithmetic is designed further for the computation of these transforms using the common-core algorithm. The proposed scheme not only leads to a systolic-like regular and modular hardware for computing these transforms, but also offers significant improvement in area-time efficiency over the existing structures. The structure proposed here is devoid of complicated input/output mapping and does not involve any complex control. Unlike the convolution-based structures, it does not restrict the transform length to be a prime or multiple of prime and can be utilized as a reusable core for cost-effective, memory-efficient, high-throughput implementation of either of these transforms     

A New Hand-Held Microsystem Architecture for Biological Analysis

This paper presents a hand-held microsystem based on new fully integrated magnetoresistive biochips for biomolecular recognition (DNA hybridization, antibody antigen interaction, etc.). Magnetoresistive chip surfaces are chemically treated, enabling the immobilization of probe biomolecules such as DNA or antibodies. Fluid handling is also integrated in the biochip. The proposed microsystem not only integrates the biochip, which is an array of 16times16 magnetoresistive sensors, but it also provides all the electronic circuitry for addressing and reading out each transducer. The proposed architecture and circuits were specifically designed for achieving a compact, programmable and portable microsystem. The microsystem also integrates a hand-held analyzer connected through a wireless channel. A prototype of the system was already developed and detection of magnetic nanoparticles was obtained. This indicates that the system may be used for magnetic label based bioassays     

Analysis and architecture design of variable block-size motion estimation for H.264/AVC

Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory.     

WiFi access point pricing as a dynamic game

We study the economic interests of a wireless access point owner and his paying client, and model their interaction as a dynamic game. The key feature of this game is that the players have asymmetric information - the client knows more than the access provider. We find that if a client has a "web browser" utility function (a temporal utility function that grows linearly), it is a Nash equilibrium for the provider to charge the client a constant price per unit time. On the other hand, if the client has a "file transferor" utility function (a utility function that is a step function), the client would be unwilling to pay until the final time slot of the file transfer. We also study an expanded game where an access point sells to a reseller,which in turn sells to a mobile client and show that if the client has a web browser utility function, that constant price is a Nash equilibrium of the three player game. Finally, we study a two player game in which the access point does not know whether he faces a web browser or file transferor type client, and show conditions for which it is not a Nash equilibrium for the access point to maintain a constant price.     

A power-driven multiplication instruction-set design method for ASIPs

This paper presents a novel power-driven multiplication instruction-set design method for application-specific instruction-set processors (ASIPs). Based on a dual-and-configurable-multiplier structure, our proposed method devises a multiplication instruction set for low-power ASIPs. Our method exploits the execution sequences of multiplication instructions and effective bit widths of variables to reduce power consumed by redundant multiplication bits while minimizing the multiplication execution time. Experimental results on a set of DSP programs demonstrate that our proposed method achieves significant power reduction (up to 18.53%) and execution time improvement (up to 10.43%) with 18% area overhead.