Device and circuit level suppression techniques for random-dopant-induced static noise margin fluctuation in 16-nm-gate SRAM cell

In this study, a three-dimensional “atomistic” coupled device-circuit simulation is performed to explore the impact of process-variation-effect (PVE) and random-dopant-fluctuation (RDF) on static noise margin (SNM) of 16-nm complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) cells. Fluctuation suppression approaches, based on circuit and device viewpoints, are further implemented to examine the associated characteristics in 16-nm-gate SRAM cells. From the circuit viewpoint, the SNM of 8T planar SRAM is enlarged to 230 mV and the variation of SNM (σ_SNM) is reduced to 22 mV at a cost of 30% extra chip area. As for device level improvement, silicon-on-insulator (SOI) FinFETs replaced the planar MOSFETs in 6T SRAM is further examined. The SNM of 6T SOI FinFETs SRAM is 125 mV and the σ_SNM is suppressed significantly to 5.4 mV. However, development of fabrication process for SOI FinFET SRAM is crucial for sub-22 nm technology era.     

A process simplification scheme for fabricating CMOS polycrystalline-Si thin film transistors

A process simplification scheme for fabricating CMOS poly-Si thin-film transistors (TFTs) has been pro-posed, which employs large-angle-tilt-implantation of dopant through a gate sidewall spacer (LATITS). By this LATITS scheme, a lightly doped drain region under the oxide spacer is formed by low-dose tilt implantation of phosphorus (orboron) dopant through the spacer, and then the n+-source/drain (n+-S/D) (or p+-S/D) region is formed via using the same photo-mask layer during CMOS integration. For both n-TFT and p-TFT devices, as compared to the sample with conventional single n+-S/D (or p+-S/D) structure, the LATITS scheme can cause an obviously smaller leakage current, due to more gradual dopant distribution and thus smaller electric field. In addition, the resultant on-state currents only show slight degradation for the LATITS scheme, As a result, by the LATITS scheme, CMOS poly-Si TFT devices with an on/off current ratio well above 8 orders may be achieved without needing extra photo-mask layers during CMOS integration.     

Nanotechnology enables a new memory growth model

As we enter the nanotechnology era, a big shift in paradigm comes to the memory industry. The traditional computer industry for dynamic RAM is expected to mature its memory-bit consumption with a relatively low growth rate. Meanwhile, the memory consumption and high-density memory usage in mobile handsets and digital consumer applications will grow very fast. For these new applications, NAND Flash memory will be the key enabling technology and its easy scaling and multibit/cell capabilities require a new memory growth model. The well-known Moore's law still holds for most cases after the quarter-century history of the integrated circuit industry. However, the paradigm shift in the memory industry requires a new memory growth model: "a twofold increase per year in memory density." This paper will cover some details of recent memory technologies, application trends, and the proposed new memory growth model.     

Microparticle‐Based Soft Electronic Devices: Toward One‐Particle/One‐Pixel

While microparticle (MP) assemblies have long attracted academic interest, few practical applications of assembled MPs have been achieved because of technological difficulties related to MP synthesis, MP position registration, and the absence of device concepts. The precise positioning of functional MPs in a proper stencil can produce flexible/stretchable electronic devices, even when the MPs themselves are rigid. In recent years, remarkable progress has been made in the programmable position registration of MPs, production of functional MPs, and concepts for MP‐based, pixel‐type electronic devices. This progress report reviews the recent technological advances in MP assembly and discusses the technological challenges preventing the realization of the one‐particle/one‐pixel concept.     

Parallel optical transmitter module using angled fibers and a V-grooved silicon optical bench for VCSEL array

We propose an advanced structure of optical subassembly (OSA) for packaging of the vertical-cavity surface-emitting laser (VCSEL) array, using (111) facet mirror of the V-groove ends formed in a silicon optical bench (SiOB) and angled fiber apertures. The feature of our OSA can provide a low optical crosstalk between neighboring channels, a low feedback reflection, and a large misalignment tolerance along the V-groove. We describe the optimized design of fiber angle, VCSEL position, and fiber position. The fabricated OSA structure consists of 12 channels of angled fiber array, 54.7/spl deg/ V-grooves, Au-coated mirrors on (111) end facet of the V-grooves, and flip-chip-bonded VCSEL array on a SiOB. In this structure, the beam emitted from the VCSEL is deflected at the 54.7/spl deg/ mirror of (111) end facet and propagated into the angled fiber. The angled fiber array was polished by 57/spl deg/. Fabricated OSAs showed a coupling efficiency of 30%-50% that is 25 times larger than that obtained from an OSA with a vertically flat fiber array. Our OSA showed large misalignment tolerance of about 90 /spl mu/m along the longitudinal direction in the V-groove. We fabricated a parallel optical transmitter module using the OSA and demonstrated 12 channels /spl times/2.5 Gb/s data transmission with a clear eye diagram.     

Broad-band erbium-doped fiber amplifier with double-passconfiguration

We demonstrate a broad-band silica-based erbium-doped fiber amplifier (EDFA) with double-pass configuration. The signal gain and noise figure are obtained more than 24 dB and less than 6 dB, respectively, for 1526-1562 nm and 1569-1605 nm. The same signal gain can be achieved with 53% less pump power and 45% shorter erbium-doped fiber length, compared to a conventional parallel type EDFA. Furthermore, the noise figure and power conversion efficiency are improved for the wavelength range     

Unified VLSI systolic array design for LZ data compression

Hardware implementation of data compression algorithms is receiving increasing attention due to exponentially expanding network traffic and digital data storage usage. In this paper, we propose several serial one-dimensional and parallel two-dimensional systolic-arrays for Lempel-Ziv data compression. A VLSI chip implementing our optimal linear array is fabricated and tested. The proposed array architecture is scalable. Also, multiple chips (linear arrays) can be connected in parallel to implement the parallel array structure and provide a proportional speedup     

Performance Enhancement of Hybrid TDOA/AOA Using Multipath Delay Estimation

Wireless Personal Communications - Wireless solar blind ultraviolet (UV) scattering communication is a new type of atmosphere optics communication technology with the important and potential...     

3D Localization for Launch Vehicle Using Virtual TOA and AOA of Ground Stations

Wireless Personal Communications - Generally, a ground telemetry station for a launch vehicle (LV) includes a tracking function only; therefore, position measurements for LV depend on received...