Analysis and Synthesis of Double-Sided Parallel-Strip Transitions

Antenna feeders, mixers, and filters made in double-sided parallel-strip technology usually must be adapted to unbalanced lines like the microstrip structure, needing transitions from asymmetric to symmetric waveguides (baluns). In this paper, we propose a new method for the evaluation of a generic tapered balun based on a conformal-mapping technique and an integral equation. This method, along with the use of an optimization technique such as genetic algorithms, allows for quick evaluation of the return losses of any tapered balun and the synthesizing of specific shapes to achieve desired responses in terms of return losses or impedance values.      

A medicinal-chemistry-guided approach to selective and druglike sigma 1 ligands

Based on a medicinal-chemistry-guided approach, three novel series of druglike cycloalkyl-annelated pyrazoles were synthesized and display high affinity (pKi>8) for the sigma1 receptor. Structure-affinity relationships were established, and the different scaffolds were optimized with respect to sigma1 binding and selectivity versus the sigma2 receptor and the hERG channel, resulting in selective compounds that have Ki values (for sigma1) in the subnanomolar range. Selected compounds were screened for cytochrome P450 inhibition (CYP1A2, CYP2A6, CYP2B6, CYP2C8, CYP2C9, CYP2C19, CYP2D6, CYP2E1, CYP3A4), metabolic stability (rat and human liver microsomes), and cell-membrane permeability (Caco-2). They showed favorable in vitro ADME properties as well as favorable calculated druglike and experimental physicochemical properties. Furthermore, compounds 7 f and 17 a, for example, displayed high selectivity (affinity) for the sigma1 receptor against a wide range of other receptors (>60). With these valuable tool compounds in hand, we are further exploring the role of the sigma1 receptor in relevant animal models corresponding to such medicinal indications as drug abuse, pain, depression, anxiety, and psychosis.     

Adding value to design and test through education: What are the challenges?

THE 6TH IEEE Latin American Test Workshop (LATW 05), took place from 30 March to 2 April 2005 in Salvador, Brazil. The workshop included a panel discussion on the challenges for modern design and test education, which attracted much attention from the audience.     

INL and DNL estimation based on noise for ADC test

This paper presents the linearity characterization of an analog-to-digital converter (ADC). The input signal is noise, which allows low analog area overhead for built-in self-test (BIST). The linearity error estimation is proposed based on the spectral analysis of only the output of the converter. This paper presents the underlying theory and practical results supporting the effectiveness of the proposed method.     

Optimum design of a banked memory with power management for wireless sensor networks

Wireless Networks - The ever-increasing complexity of applications covered by wireless sensor networks (WSNs) demands for increasing memory size, which in turn increases the power drain. It is well...     

BTEK新科技导览中心，扎穆迪奥，比斯卡亚，西班牙

BTEK新科技导览中心被设计成为一座里程碑．一个景观的基准点。它由两座相互独立的金字塔式建筑物构成第一座整体呈黑色，由地面升起．体量较重，由3个金属立面构成．屋顶完全由太阳能板组成。     

Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs

Processor cores embedded in systems-on-a-chip (SoCs) are often deployed in critical computations, and when affected by faults they may produce dramatic effects. When hardware hardening is not cost-effective, software implemented hardware fault tolerance (SIHFT) can be a solution to increase SoCs’ dependability, but it increases the time for running the hardened application, as well as the memory occupation. In this paper we propose a method that eliminates the memory overhead, by exploiting a new approach to instruction hardening and control flow checking. The proposed method hardens an application online during its execution, without the need for introducing any change in its source code, and is non-intrusive, since it does not require any modification in the main processor’s architecture. The method has been tested with two widely used architectures: a microcontroller and a RISC processor, and proven to be suitable for hardening SoCs against transient faults and also for detecting permanent faults.     

Reducing Test Time Using an Enhanced RF Loopback

This work presents a method to improve the loopback test used in RF transceivers. The approach is targeted to the System-On-Chip environment, being able to reuse system resources in order to minimize the test overhead. An RF sampler is used during loopback operation, allowing observation of spectral characteristics of the RF signal. While able to improve the overall observability of the RF signal path, faster diagnosis than conventional loopback tests is achieved thanks to a large reduction in the number of transmitted symbols. Theoretical analysis and practical results for a prototype transceiver operating at 846 MHz are presented. It is shown that a significant test time reduction is achievable considering bit error rate tests for common digital modulation schemes.