A theoretical study of the performance of sub-micron MOSFET devices in the presence of edge potential

In the present communication we have presented a detailed theoretical analysis of the performance of the sub-micron device in the presence of the discontinuity at the Si–SiO₂ interface. It is assumed that due to interface discontinuity a potential develops at the edges (Source/Drain) in addition to the built-in-potential. This potential, called Edge Potential, measures directly the extent of the interface roughness. The effect of this potential is more critical in the case of short channel device where drain and source are in close proximity. Our analysis shows that the discontinuity is dominant at the edges but not in the channel. Drive current as well as saturation transconductance decreases in the presence of edge potential. These results suggest that the performance of the device degrades due to the interface roughness. Effect of interface roughness near the edges can be reduced at high gate voltage but it will result more interface roughness scattering.     

Combating/eliminating dispersion-induced fading using suppressed carrier link for OFDM signal

We investigate the performance of 20-GHz radio over fibre (RoF) system having orthogonal frequency division multiplexed (OFDM) as radio signal using two modulation techniques – balanced detection for intensity modulation direct detection (IMDD) and coherent heterodyne detection suppressed carrier (SC) modulation. Dispersion-induced power fading is seen in conventional IMDD links due to the dependence of dispersion over frequency-dependent refractive index of the fibre. SC link is seen to compensate the power fading by terminating the direct current and even-order harmonics with the suppression of carrier along with balanced detection.     

Programmable memory cell using quantum confined Stark effect in multi-quantum well heterojunction bipolar transistor

A three terminal bistable programmable memory cell which can be read either optically or electrically is proposed and demonstrated. The device is based on using Stark effect of the excitonic transitions in a multi-quantum well base region of a heterojunction bipolar transistor. The single device can be flipped (and held) from low transmittance (high voltage) to high transmittance (low voltage) state and vice versa by a varying base current signal.<>     

Through‐the‐glass spectroscopic ellipsometry for analysis of CdTe thin‐film solar cells in the superstrate configuration

Polycrystalline CdS/CdTe thin‐film solar cells in the superstrate configuration have been studied by spectroscopic ellipsometry (SE) using glass side illumination. In this measurement method, the first reflection from the ambient/glass interface is rejected, whereas the second reflection from the glass/film‐stack interface is collected; higher order reflections are also rejected. The SE analysis incorporates parameterized dielectric functions ε for solar cell component materials obtained by in situ and variable‐angle SE. In the SE analysis of the complete cells, a step‐wise procedure ranks the fitting parameters, including thicknesses and those defining the spectra in ε, according to their ability to reduce the root‐mean‐square deviation between the simulated and measured SE spectra. The best fit thicknesses from this analysis are found to be consistent with electron microscopy. Based on the SE results, the solar cell quantum efficiency (QE) can be simulated without any free parameters, and comparisons with measured QE enable optical model refinements as well as identification of optical and electronic losses. These capabilities have wide applications in photovoltaic module mapping and in‐line monitoring. Copyright © 2016 John Wiley & Sons, Ltd.     

Study of meander line delay in circuit boards

A moment technique is used to determine the propagation delay in meander (serpentine) delay lines located in printed circuit boards of computer systems. The full three-dimensional effects of the meander structure including signal line thickness, right-angle bends, and skin-effect are included. A set of delay lines having different pitches are considered, and results are calculated and compared to those from two-dimensional simulations, other commercial codes, analytic formulas in the literature, and experimental measurements. Based on the consistency of the results and sensitivity analyses involving numerical gridding and frequency content, the delays calculated for meander lines situated in a homogeneous medium are accurate to better than a few tenths of a percent     

Molecular beam epitaxial growth of HgCdTe on CdZnTe(311)B

A series of n-type, indium-doped Hg_1−xCd_xTe (x∼0.225) layers were grown on Cd_0.96Zn_0.04Te(311)B substrates by molecular beam epitaxy (MBE). The Cd_0.96Zn_0.04Te(311)B substrates (2 cm × 3 cm) were prepared in this laboratory by the horizontal Bridgman method using double-zone-refined 6N source materials. The Hg_1−xCd_xTe(311)B epitaxial films were examined by optical microscopy, defect etching, and Hall measurements. Preliminary results indicate that the n-type Hg_1−xCd_xTe(311)B and Hg_1−xCd_xTe(211)B films (x ∼ 0.225) grown by MBE have comparable morphological, structural, and electrical quality, with the best 77 K Hall mobility being 112,000 cm²/V·sec at carrier concentration of 1.9×10⁺¹⁵ cm⁻³.     

Dose control circuit for digital electrostatic electron-beam array lithography

This paper demonstrates a technique for controlling the electron emission of an array of field emitting vertically aligned carbon nanofibers (VACNFs). An array of carbon nanofibers (CNF) is to be used as the source of electron beams for lithography purposes. This tool is intended to replace the mask in the conventional photolithography process by controlling their charge emission using the “Dose Control Circuitry” (DCC). The large variation in the charge emitted between CNFs grown in identical conditions forced the controller design to be based on fixed dose rather than on fixed time. Compact digital control logic has been designed for controlling the operation of DCC. This system has been implemented in a 0.5 μm CMOS process. Chandra Sekhar A. Durisety received his B.E. (Hons.) Instrumentation from Birla Institute of Technology and Sciences, Pilani, India in 1997 and his M.S in Electrical Engineering from University of Tennessee, Knoxville in 2002. Since 2003, he has been working towards his Ph.D degree also in Electrical Engineering at Integrated Circuits and Systems Lab (ICASL), University of Tennessee, Knoxville. He joined Wipro Infotech Ltd, Global R & D, Bangalore, India in 1997, where he designed FPGA based IPs for network routers. Since 1999, he was involved in the PCI bridge implementation at CMOS chips Inc, Santa Clara, CA, and the test bench development for Sony’s MP3 player, while at Toshiba America Electronic Components Inc., San Jose, CA. His research interests include multi-stage amplifiers, data converters, circuits in SOI and Floating Gate Devices. Rajagopal Vijayaraghavan received the B.E degree in electronics and communication engineering from Madras University in 1998 and the M.S degree in electrical engineering from the University of Texas, Dallas in 2001.He is currently working towards the Ph.D degree in electrical engineering at the University of Tennessee. His research interest is in the area of CMOS Analog and RF IC design. His current research focuses on LNAs and VCOs using SOI based MESFET devices. Lakshmipriya Seshan was born in Trivandrum, India on April 30, 1979. She received her B.tech in Electronincs & Communication Engg from Kerala University, India in June 2000 and M.S in Electrical Engg from University of Tennessee in 2004. In 2004, she joined Intel Corporation as an Analog Engineer, where she is engaged in the design of low power, high speed analog circuits for various I/O interface topologies. Syed K. Islam received his B.Sc. in Electrical and Electronic Engineering from Bangladesh University of Engineering and Technology (BUET) and M.S. and Ph.D. in Electrical and Systems Engineering from the University of Connecticut. He is presently an Associate Professor in the Department of Electrical and Computer Engineering at the University of Tennessee, Knoxville. Dr. Islam is leading the research efforts of the Analog VLSI and Devices Laboratory at the University of Tennessee. His research interests are design, modeling and fabrication of microelectronic/optoelectronic devices, molecular scale electronics and nanotechnology, biomicroelectronics and monolithic sensors. Dr. Islam has numerous publications in technical journals and conference proceedings in the areas of semiconductors devices and circuits. Benjamin J. Blalock received his B.S. degree in electrical engineering from The University of Tennessee, Knoxville, in 1991 and the M.S. and Ph.D. degrees, also in electrical engineering, from the Georgia Institute of Technology, Atlanta, in 1993 and 1996 respectively. He is currently an Assistant Professor in the Department of Electrical and Computer Engineering at The University of Tennessee where he directs the Integrated Circuits and Systems Laboratory (ICASL). His research focus there includes analog IC design for extreme environments (both wide temperature and radiation immune), multi-gate transistors and circuits on SOI, body-driven circuit techniques for ultra low-voltage analog, mixed-signal/mixed-voltage circuit design for systems-on-a-chip, and bio-microelectronics. Dr. Blalock has co-authored over 60 published refereed papers. He has also worked as an analog IC design consultant for Cypress Semiconductor Corp. and Concorde Microsystems Inc.     

High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.     

Ge-Rich (70%) SiGe Nanowire MOSFET Fabricated Using Pattern-Dependent Ge-Condensation Technique

A top-down approach of forming SiGe-nanowire (SGNW) MOSFET, with Ge concentration modulated along the source/drain (Si_0.7Ge_0.3) to channel (Si_0.3Ge_0.7) regions, is presented. Fabricated by utilizing a pattern-size-dependent Ge-condensation technique, the SGNW heterostructure PMOS device exhibits 4.5times enhancement in the drive current and transconductance (G_m) as compared to the homojunction planar device (Si_0.7Ge_0.3). This large enhancement can be attributed to several factors including Omega-gated nanowire structure, enhanced hole injection efficiency (due to valence band offset), and improved hole mobility (due to compressive strain and Ge enrichment in the nanowire channel).     

Water-table variation in a sloping aquifer due to random recharge

Variation in the level of the water table is closely linked with recharge. Therefore, any uncertainty associated with the recharge rate is bound to affect the nature of the water-table fluctuation. In this note, a ditch-drainage problem of a sloping aquifer is considered to investigate the effect of uncertainty in the recharge rate on water-table fluctuation. The rate of recharge is taken as an exponentially decaying function with its decay constant as a Gaussian random variable. Expressions for the first two moments of the water-table height, i.e. mean and standard deviation, are presented. By using these expressions, the effect of uncertainty in the recharge rate on the water-table fluctuation has been analyzed with the help of a numerical example.