A 16-Bit by 16-Bit MAC Design Using Fast 5:3 Compressor Cells

3:2 counters and 4:2 compressors have been widely used for multiplier implementations. In this paper, a fast 5:3 compressor is derived for high-speed multiplier implementations. The fast 5:3 compression is obtained by applying two rows of fast 2-bit adder cells to five rows in a partial product matrix. As a design example, a 16-bit by 16-bit MAC (Multiply and Accumulate) design is investigated both in a purely logical gate implementation and in a highly customized design. For the partial product reduction, the use of the new 5:3 compression leads to 14.3% speed improvement in terms of XOR gate delay. In a dynamic CMOS circuit implementation using 0.225 m bulk CMOS technology, 11.7% speed improvement is observed with 8.1% less power consumption for the reduction tree.     

Bandwidth Adaptation Algorithms for Adaptive Multimedia Services in Mobile Cellular Networks

The fluctuation of available link bandwidth in mobilecellular networks motivates the study of adaptive multimediaservices, where the bandwidth of an ongoing multimedia call can bedynamically adjusted. We analyze the diverse objectives of theadaptive multimedia framework and propose two bandwidth adaptationalgorithms (BAAs) that can satisfy these objectives. The firstalgorithm, BAA-RA, takes into consideration revenue and``anti-adaptation' where anti-adaptation means that a user feelsuncomfortable whenever the bandwidth of the user's call ischanged. This algorithm achieves near-optimal total revenue withmuch less complexity compared to an optimal BAA. The secondalgorithm, BAA-RF, considers revenue and fairness, and aims at themaximum revenue generation while satisfying the fairnessconstraint defined herein. Comprehensive simulation experimentsshow that the difference of the total revenue of BAA-RA and thatof an optimal BAA is negligible. Also, numerical results revealthat there is a conflicting relationship between anti-adaptationand fairness.     

CW operation and threshold characteristics of all-monolithic InAlGaAs 1.55-/spl mu/m VCSELs grown by MOCVD

We demonstrate an all-monolithic metal-organic chemical vapor epitaxy (MOCVD)-grown 1.55-/spl mu/m vertical-cavity surface-emitting laser operating continuous wave up to 35/spl deg/C. The structure is based on the InAlGaAs-InP material system grown by a single step of MOCVD. Wet oxidation of a strained In/sub 0.4/Al/sub 0.6/As layer is used for the current confinement. The threshold current, threshold voltage and the external quantum efficiency at room temperature are about 1.6 mA, 2.3 V, and 5.4%, respectively.     

A physics-based GaAs PHEMT noise model for low drain bias operation using characteristic potential method

A new physics-based noise model of a GaAs PHEMT is developed using the characteristic potential method (CPM). The model calculates the intrinsic noise current sources using CPM. Combined with the extrinsic noise parameters extracted from the measured S-parameters, the model reproduces four noise parameters of the device accurately under low drain bias voltages without using any fitting parameters. The model is verified with a 0.2-/spl mu/m GaAs PHEMT and shows excellent agreement with the measurements for all the noise parameters up to a drain voltage of 1 V Also, the proposed method allows the simulation of the microscopic noise distribution and thus allows one to obtain a physical understanding of noise mechanisms inside the device.     

A simple and analytical parameter-extraction method of a microwaveMOSFET

A simple and accurate parameter-extraction method of a high-frequency small-signal MOSFET model including the substrate-related parameters and nonreciprocal capacitors is proposed. Direct extraction of each parameter using a linear regression approach is performed by Y-parameter analysis on the proposed equivalent circuit of the MOSFET for high-frequency operation. The extracted results are physically meaningful and good agreement has been obtained between the simulation results of the equivalent circuit and measured data without any optimization. Also, the extracted parameters, such as g_m and g_ds, match very well with those obtained by DC measurement     

Switched‐Capacitor Variable Gain Amplifier with Operational Amplifier Preset Technique

We present a novel operational amplifier preset technique for a switched‐capacitor circuit to reduce the acquisition time by improving the slewing. The acquisition time of a variable gain amplifier (VGA) using the proposed technique is reduced by 30% compared with a conventional one; therefore, the power consumption of the VGA is decreased. For additional power reduction, a programmable capacitor array scheme is used in the VGA. In the 0.13 μm CMOS process, the VGA, which consists of three‐stages, occupies 0.33 mm² and dissipates 19.2 mW at 60 MHz with a supply voltage of 1.2 V. The gain range is 36.03 dB, which is controlled by a 10‐bit control word with a gain error of ±0.68 LSB.     

Phase-separated polydimethylsiloxane as a dielectric surface treatment layer for organic field effect transistors

We suggest a novel method for treating the surfaces of dielectric layers in organic field effect transistors (OFETs). In this method, a blend of poly(9,9-dioctylfluorene-alt-bithiophene) (F8T2) and dimethylsiloxane (DMS) with a curing agent is spin coated onto the surface of a dielectric substrate, silicon oxide (SiO₂), and then thermally cured. X-ray photoelectron spectroscopy, contact angle measurements, and morphology analysis were used to show that the hydrophilic DMS layer is preferentially adsorbed on the SiO₂ substrate during the spin coating process. After thermal curing, the bottom DMS layer becomes a hydrophobic PDMS layer. This bottom PDMS layer becomes thinner during curing due to the upward motion of the hydrophobic PDMS molecules. The FET mobility of the cured system was 10^?2 cm²/Vs, which is similar to that of polymeric semiconductors on octadecyltrichlorosilane treated SiO₂ dielectric layers. We also discuss the possibility of using this blend method to increase the air-stability of polymeric semiconductors.     

Functionally Antagonistic Hybrid Electrode with Hollow Tubular Graphene Mesh and Nitrogen‐Doped Crumpled Graphene for High‐Performance Ionic Soft Actuators

Ionic soft actuators, which exhibit large mechanical deformations under low electrical stimuli, are attracting attention in recent years with the advent of soft and wearable electronics. However, a key challenge for making high‐performance ionic soft actuators with large bending deformation and fast actuation speed is to develop a stretchable and flexible electrode having high electrical conductivity and electrochemical capacitance. Here, a functionally antagonistic hybrid electrode with hollow tubular graphene meshes and nitrogen‐doped crumpled graphene is newly reported for superior ionic soft actuators. Three‐dimensional network of hollow tubular graphene mesh provides high electrical conductivity and mechanically resilient functionality on whole electrode domain. On the contrary, nitrogen‐doped wrinkled graphene supplies ultrahigh capacitance and stretchability, which are indispensably required for improving electrochemical activity in ionic soft actuators. Present results show that the functionally antagonistic hybrid electrode greatly enhances the actuation performances of ionic soft actuators, resulting in much larger bending deformation up to 620%, ten times faster rise time and much lower phase delay in a broad range of input frequencies. This outstanding enhancement mostly attributes to exceptional properties and synergistic effects between hollow tubular graphene mesh and nitrogen‐doped crumpled graphene, which have functionally antagonistic roles in charge transfer and charge injection, respectively.     

A fully integrated switched-capacitor DC–DC converter with hybrid output regulation

In this paper, we propose a fully integrated switched-capacitor (SC) DC–DC converter with hybrid output regulation that allows a predictable switching noise spectrum. The proposed hybrid output regulation method is based on the digital capacitance modulation for fine regulation and the automatic frequency scaling for coarse regulation. The automatic frequency scaler and on-chip current sensor are implemented to adjust the switching frequency at one of the frequencies generated by a binary frequency divider with change in load current. Thus, the switching noise spectrum of the proposed SC DC–DC converter can be predicted over the entire load range. In addition, the bottom-plate losses due to the parasitic capacitances of the flying capacitors and the gate-drive losses due to the gate capacitances of switches are reduced at light load condition since the switching frequency is automatically adjusted. The proposed SC DC–DC converter was implemented in a 0.13 µm CMOS process with 1.5 V devices, and its measurement results show that the peak efficiency and the efficiency at light load condition are 69.2% and higher than 45%, respectively, while maintaining a predictable switching noise spectrum.