Initial and boundary conditions in multidimensional wave digital filter algorithms for plate vibration

Recently, multidimensional wave digital filter (MDWDF) structures have been proposed for the modeling of plate vibration problems. In this paper, we discuss how initial and boundary conditions may be properly embedded into such an algorithm in terms of the state quantities that are an integral part of the algorithm. Due to the essential feature of fully-local interconnectivity in the MDWDF model, different types of boundary conditions can be easily satisfied in a very simple and efficient manner. Instead of remodifying the whole algorithm, usually required by finite elements based methods, boundary conditions in terms of state outputs are simply attached to the model. This feature is especially useful when dealing with the mixed-edges boundary conditions frequently encountered in practice. Graphical results obtained from implementing the MDWDF algorithm are given to further demonstrate the capacities of the method in efficiently handling a fourth-order Mindlin plate vibration system with various types of boundary conditions.     

A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications

A CMOS local oscillator using a programmable delayed-lock loop based frequency multiplier is present in this paper. The maximum measured output frequency is 1.2 GHz. The frequency of the output clock is 8/spl times/ to 10/spl times/ of an input reference clock between 100 to 150 MHz at simulation. No LC-tank is used in the proposed design such that the power dissipation as well as the active area is drastically reduced. The design is carried out by TSMC 1P5M 0.25 /spl mu/m CMOS process at 2.5 V power supply. The average lock time is optimally shortened by initializing the start-up voltage of the voltage-controlled delay tap line at the midway of the working range. Meanwhile, the power dissipation is 52.5 mW at 1.2 GHz output.     

Characterization of the Ultrathin HfO2 and Hf-Silicate Films Grown by Atomic Layer Deposition

The physical properties of HfO₂ and Hf-silicate layers grown by the atomic layer chemical vapor deposition are characterized as a function of the Hf concentration and the annealing temperature. The peaks of Fourier transform infrared spectra at 960, 900, and 820 cm_-1 originate from Hf-O-Si chemical bonds, revealing that a Hf-silicate interfacial layer began to form at the HfO₂/SiO ₂ interface after post deposition annealing process at 600 degC for 1 min. Moreover, the intensity of the peak at 750 cm^-1 can indicate the degree of crystallization of HfO₂. The formed Hf-silicate layer between HfO² and SiO² is also confirmed by X-ray photoelectron spectroscopy     

A full-wave mixed potential mode-matching method for the analysisof planar or quasi-planar transmission lines

A full-wave mixed potential mode-matching method is presented for the analysis of planar and/or quasi-planar transmission lines. The transmission lines studied consist of layered (stratified) and nonlayered dielectric substrates and metal strips of finite thickness. The y-directed hybrid transverse electric (TE) and transverse-magnetic (TM) Hertzian potentials, perpendicular to the interfaces between each layered region, are employed in the layered regions. The nonlayered regions consist of dielectric step discontinuities that destroy the layered configuration in the horizontal plane, allowing a systematic and easy to handle full-wave formulation of the transmission line problem. The relative convergence criterion needs to be satisfied to obtain accurate electromagnetic field solutions. Theoretical results are in very good agreement with published data for various transmission line structures. Applications of the formulation to the proximity effects of microstrip and microslab lines are illustrated     

Low-frequency noise in TaSiN/HfO/sub 2/ nMOSFETs and the effect of stress-relieved preoxide interfacial layer

Low-frequency noise characteristics are reported for TaSiN-gated n-channel MOSFETs with atomic-layer deposited HfO/sub 2/ on thermal SiO/sub 2/ with stress-relieved preoxide (SRPO) pretreatment. For comparison, control devices were also included with chemical SiO/sub 2/ resulting from standard Radio Corporation of America clean process. The normalized noise spectral density values for these devices are found to be lower when compared to reference poly Si gate stack with similar HfO/sub 2/ dielectric. Consequently, a lower oxide trap density of /spl sim/4/spl times/10/sup 17/ cm/sup -3/eV/sup -1/ is extracted compared to over 3/spl times/10/sup 18/ cm/sup -3/eV/sup -1/ values reported for poly Si devices indicating an improvement in the high-/spl kappa/ and interfacial layer quality. In fact, this represents the lowest trap density values reported to date on HfO/sub 2/ MOSFETs. The peak electron mobility measured on the SRPO devices is over 330 cm/sup 2//V/spl middot/s, much higher than those for equivalent poly Si or metal gate stacks. In addition, the devices with SRPO SiO/sub 2/ are found to exhibit at least /spl sim/10% higher effective mobility than RCA devices, notwithstanding the differences in the high-/spl kappa/ and interfacial layer thicknesses. The lower Coulomb scattering coefficient obtained from the noise data for the SRPO devices imply that channel carriers are better screened due to the presence of SRPO SiO/sub 2/, which, in part, contributes to the mobility improvement.     

70 dB Dynamic Range CMOS Wideband Digital Variable Gain Amplifier for AGC in DVB-T/H Receivers

This paper presents a novel variable gain amplifier (VGA) design which is applied in the automatic gain control loop of digital video broadcasting (DVB) receivers designed for standards DVB-T/H. The VGA is composed of three cascaded tunable gain stages to provide a 70 dB dynamic range with 2 dB gain steps. Each gain stage is based on a digital variable gain amplifier (DVGA) which is composed of a plurality of gain blocks (GBs) and a fully differential degeneration amplifier (FDDA). The GBs of the DVGA are digitally controlled current mirrors. A common-mode feedback circuitry is used to stabilize the FDDA by providing a stable common-mode voltage. Physical measurements on silicon show that the gain error is merely 0.55 dB given a 70 dB tuning range. This work was supported by National Science Council, Taiwan, under contract nos. NSC96-2628-E-110-019 and NSC96-2920-E-110-001.     

Concurrent Zero Knowledge, Revisited

We provide a more general and, in our eyes, simpler variant of Prabhakaran, Rosen and Sahai’s (FOCS ’02, pp. 366–375, 2002) analysis of the concurrent zero-knowledge simulation technique of Kilian and Petrank (STOC ’01, pp. 560–569, 2001).     

Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems

In this paper, a novel reconfigurable discrete wavelet transform processor architecture is proposed to meet the diverse computing requirements of future generation multimedia SoC. The proposed architecture mainly consists of reconfigurable processing element array and reconfigurable address generator, featuring dynamically reconfigurable capability where the wavelet filters and wavelet decomposition structures can be reconfigured as desired at run-time. The lifting-based reconfigurable processing element array possesses better computation efficiency than convolution-based architectures, and a systematic design method is provided to generate the hardware configurations of different wavelet filters for it. The reconfigurable address generator handles flexible address generation for data I/O access in different wavelet decomposition structures. A prototyping chip has been fabricated by TSMC 0.35 μm 1P4M CMOS process. At 50 MHz, this chip can achieve at most 100 M pixels/sec transform throughput, together with energy efficiency and unique reconfigurability features, proving it to be a universal and extremely flexible computing engine for heterogeneous reconfigurable multimedia systems.Po-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems.Chao-Tsung Huang was born in Kaohsiung, Taiwan, R.O.C., in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. He currently is working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for signal processing systems.Liang-Gee Chen (S’84–M’86–SM’94–F’01) received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively. In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of VLSI Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration

This paper presents a self-testing and calibration technique for the embedded successive approximation register (SAR) analog-to-digital converter (ADC) in system-on-chip (SoC) designs. We first proposed a low cost design-for-test (DfT) technique that estimates the SAR ADC performance before and after calibration by characterizing its digital-to-analog converter (DAC) capacitor weights (bit weights). Utilizing major carrier transition (MCT) testing, the required analog measurement range is only about 1 LSB; this significantly reduces test circuitry complexity. Then, we develop a fully-digital calibration technique that utilizes the extracted bit weights to correct the non-ideal I/O behavior induced by capacitor mismatch. Simulation results show that (1) the proposed testing technique achieves very high test accuracy even in the presence of large noise, and (2) the proposed calibration technique effectively improves both static and dynamic performances of the SAR ADC.     

Co‐tier downlink interference management in dense femtocell networks

With the adoption of long‐term evolution standard for 4G mobile communications, the deployment of femtocell base stations (FBSs) to cope with the surging traffic in mobile wireless communication is becoming increasingly popular. However, with the random installation of FBSs, the problem of interference among FBSs is still a challenge. In this paper, assuming the presence of a femtocell management system that can control and coordinate the densely deployed FBSs, a novel power backoff scheme is proposed that determines the appropriate transmit power of each FBS so that the interference is reduced. Simulation results for randomly deployed FBSs in an environment with shadowing using MATLAB are provided, showing that our proposed methods can effectively mitigate the co‐tier downlink interference while improving the system capacity in a densely deployed femtocell network with shared spectrum use. Quantitatively, the average interference is reduced by roughly 90% to 100% of dBm, and the average capacity is increased by more than 80%. These results attest to the effectiveness of the proposed scheme.