A gm-boosted common-gate CMOS low-noise amplifier with high P1dB

A 2.4-GHz transconductance (g_m)—boosted common gate (CG) low-noise amplifier (LNA) with a high 1-dB compression point (P1dB) is proposed. To overcome the constraint of conventional CG LNA for input-mismatching, RF filters consisting of band-stop and high-pass filter are used as a load and inter-stage matching components, respectively. Therefore, the g _m can be freely increased for a high gain and low noise figure (NF) without decreasing input impedance. Moreover, the linearity is also enhanced because band-stop filter load can reduce 2nd harmonics. The fully integrated LNA implemented by 0.18-µm RF CMOS technology delivers an input P1dB of ?1 dBm, a power gain of 14.8 dB and a NF of 3.7 dB. The LNA consumes 8.2 mA at a supply voltage of 1.8 V.     

Design and analysis of novel quorum-based sink location service scheme in wireless sensor networks

Geographic routing in wireless sensor networks requires sources nodes to be aware of the location information of sinks to send their data. To provide the sink location service, quorum-based schemes have been proposed, which exploit crossing points between a quorum of a sink location announcement (SLA) message from a sink and a quorum of a sink location query (SLQ) message from a source node. For guaranteeing at least one crossing point in irregular sensor networks with void areas or irregular boundaries, the previous schemes however collect and flood the network boundary information or forward a SLA and SLQ message along the whole network boundary. In this paper, we design a novel quorum-based sink location service scheme that exploits circle and line quorums, which does not require the network boundary information and send a SLA and SLQ message along the whole network boundary. In the proposed scheme, a source node sends a SLQ message to the network center and sends another SLQ message to an edge node in the network boundary, thus generating a SLQ line quorum. On the other hand, a sink node sends a SLA message along a circle path whose center is the network center, thus forming a SLQ circle quorum. By this way, it is guaranteed that the SLQ and SLA quorums have at least one crossing point in irregular sensor networks. Both numerical analysis and extensive simulation results verify that the proposed scheme outperforms the existing schemes in terms of the delivery distance, the delivery hop count, and the energy consumption for providing sink location service.     

Large Scale Indoor Localization System Based on Wireless Sensor Networks for Ubiquitous Computing

The task of formulating an efficient system for determining the location of an object, results in the creation of a wide number of applications and services. For this reason, most wireless sensor network applications assume the availability of sensor location information. In this paper, an indoor localization scheme, which is based on synchronized sensor nodes, is proposed. It is efficient in terms of power consumption and location update rate. Furthermore, it resolves the scalability problem usually found in most conventional indoor localization systems in large scale indoor environments. The performance of the proposed scheme is evaluated through experimental implementation and is compared with the Cricket system. The results demonstrate that the proposed scheme is a promising and feasible localization system for a large scale indoor environment.     

The effects of bath composition on the morphologies of electroless nickel under-bump metallurgy on Al input/output pad

The electroless nickel plating on an aluminum input/output (I/O) pad was investigated. The aluminum pad was pretreated in a zincate solution prior to electroless nickel plating. Zinc particles on the aluminum pad gave a good adherent nickel layer. The adhesion and uniformity of zinc on the aluminum is the key factor in under-bump metallurgy (UBM). The electrode potential changes with and without zinc ions in the bath were measured to analyze the sequence of two competing reactions: zinc deposit and hydrogen evolution. The relationship between aluminum dissolution and the ratio of zinc and NaOH was investigated. The electroless nickel deposition rate was dependent on bath composition. The effects of complexing ligand and additive on the nickel deposit were analyzed. Electrode potential changes were measured with time to confirm nucleation and grain growth. Adhesion of the UBM was related to zinc-particle dissolution and nickel nucleation. The uniform nickel UBM was fabricated on a real Al I/O pad.     

Photocurable propyl-cinnamate-functionalized polyhedral oligomeric silsesquioxane as a gate dielectric for organic thin film transistors

A polyhedral oligomeric silsesquioxane (POSS)-based insulating material with photocurable propyl-cinnamate groups (POSS-CYNNAM) was designed and synthesized through simple single step reaction for use as a gate dielectric in organic thin-film transistors (OTFT). POSS-CYNNAM was soluble in common organic solvents and formed a smooth thin film after spin-casting. A thin film of POSS-CYNNAM was cross-linked and completely solidified under UV irradiation without the use of additives such as photoacid generators or photoradical initiators. ITO/insulator/Au devices were fabricated and characterized to measure the dielectric properties of POSS-CYNNAM thin films, such as leakage current and capacitance. A pentacene-based OTFT using the synthesized insulator as the gate dielectric layer was fabricated on the transparent indium tin oxide (ITO) electrode, and its performance was compared to OTFTs using thermally cross-linked poly(vinyl phenol) (PVP) as the insulator. The fabricated POSS-CYNNAM OTFT showed a comparable performance to devices based on the PVP insulator with 0.1 cm²/Vs of the field effect mobility and 4.2 × 10⁵ of an on/off ratio.     

High-performance polymer light emitting diodes with interface-engineered graphene anodes

Recently, graphene-based organic light emitting diodes (OLEDs) were successfully demonstrated using graphene as anodes. However, the graphene electrodes have not been utilized for polymer light emitting diodes (PLEDs) yet, although the simpler device structure and the solution-based fabrication process of PLEDs are expected to be more advantageous in terms of time and cost. Here we demonstrate high-performance polymer light emitting diodes (PLEDs) with simple two-layer structures using interface-engineered single-layer graphene films as anodes. The single-layer graphene synthesized by chemical vapor deposition methods was transferred onto a glass substrate utilizing an elastic stamp, and its work function was engineered by varying the duration and the power of ultraviolet ozone (UVO) treatment. Thus, we were able to optimize the contact between silver electrodes and the graphene anodes, leading to the considerable enhancement of light-emitting performance.     

A dynamic ID management protocol for CSMA/IC in ad hoc networks

Contention based MAC protocols are widely used in ad hoc networks because they are suitable, where no central control node exists. However, contention based MAC protocols waste much time because of frequent collisions and long contention times. Moreover, it is hard for them to fairly distribute medium access opportunities. As a result, the problem of unfair medium access may arise under normal network conditions. Recently, another contention based MAC protocol, named the Carrier Sense Multiple Access/ID Countdown (CSMA/IC) was proposed. CSMA/IC resolves medium access contention by comparing the IDs of contending nodes with a simple signaling process. Therefore, medium access collisions never happen as long as each node possesses a unique ID, and the time cost for contention may be smaller than any other contention based MAC protocols if the number of IDs is managed so as to be as small as possible. Furthermore, CSMA/IC may support fair medium access by manipulating the ID of each node properly. In this paper, we propose a novel dynamic ID management protocol which enables a node to acquire a unique ID without any message exchanges and fairly distributed the number of medium access opportunities to all contending nodes. The proposed protocol also makes the contention process of CSMA/IC efficient by dynamically managing the length of the ID field according to the network traffic. The simulation results show that the proposed ID management protocol significantly improves the aforementioned aspects of CSMA/IC MAC protocol compared to previous ID management schemes.     

Improvement of the cell performance in the ZnS/Cu(In,Ga)Se2 solar cells by the sputter deposition of a bilayer ZnO : Al film

ZnS is a candidate to replace CdS as the buffer layer in Cu(In,Ga)Se₂ (CIGS) solar cells for Cd‐free commercial product. However, the resistance of ZnS is too large, and the photoconductivity is too small. Therefore, the thickness of the ZnS should be as thin as possible. However, a CIGS solar cell with a very thin ZnS buffer layer is vulnerable to the sputtering power of the ZnO : Al window layer deposition because of plasma damage. To improve the efficiency of CIGS solar cells with a chemical‐bath‐deposited ZnS buffer layer, the effect of the plasma damage by the sputter deposition of the ZnO : Al window layer should be understood. We have found that the efficiency of a CIGS solar cell consistently decreases with an increase in the sputtering power for the ZnO : Al window layer deposition onto the ZnS buffer layer because of plasma damage. To protect the ZnS/CIGS interface, a bilayer ZnO : Al film was developed. It consists of a 50‐nm‐thick ZnO : Al plasma protection layer deposited at a sputtering power of 50 W and a 100‐nm‐thick ZnO : Al conducting layer deposited at a sputtering power of 200 W. The introduction of a 50‐nm‐thick ZnO : Al layer deposited at 50 W prevented plasma damage by sputtering, resulting in a high open‐circuit voltage, a large fill factor, and shunt resistance. The ZnS/CIGS solar cell with the bilayer ZnO : Al film yielded a cell efficiency of 14.68%. Therefore, the application of bilayer ZnO : Al film to the window layer is suitable for CIGS solar cells with a ZnS buffer layer. Copyright © 2012 John Wiley & Sons, Ltd.     

Power optimization of multi-level logic circuits utilizing circuit symmetries

The property of circuit symmetry has long been applied to the problem of minimizing the area and timing of multi-level logic circuits. In this paper, we focus on another important design objective, power optimization, utilizing circuit symmetries. First, we analyse and establish the relationship between several types of circuit symmetry and their applicability to reducing power consumption of the circuit, proposing a set of re-synthesis techniques utilizing the symmetries. We derive an algorithm for detecting the symmetries (among the internal signals as well as the primary inputs) on a given circuit implementation. We then propose an effective transformation algorithm to minimize power consumption using the symmetry information detected from the circuit. Unlike many other approaches, our transformation algorithm guarantees monotonic improvement in terms of switching activities, which is practically useful in that user can check the intermediate re-synthesized designs in terms of the degree of changes of power, area, timing, and the circuit structure. We have carried out experiments on MCNC benchmark circuits to demonstrate the effectiveness of our algorithm. On average we reduced the power consumption of circuits by 12% with relatively little increase of area and timing.