Hybrid cascode compensation with feedforward stage for high-speed area-efficient three-stage CMOS amplifiers

Hybrid cascode feedforward compensation (HCFC) is proposed for low-power area-efficient three stage amplifiers driving large capacitive loads. With no overhead in power or area, the total compensation capacitor is divided and shared between two internal high-speed loops instead of solely one loop as is common in prior art. Detailed analysis of HCFC shows significant improvement in terms of stability and bandwidth. This is verified for a 1.2-V amplifier driving a 500-pF capacitive load in 90-nm CMOS technology, where HCFC reduces the total capacitor size and improves the gain-bandwidth by at least 30 and 40 %, respectively, compared to the prevailing schemes.     

A novel low voltage very low power CMOS class AB current output stage with ultra high output current drive capability

In this paper a novel low voltage (LV) very low power (VLP) class AB current output stage (COS) with extremely high linearity and high output impedance is presented. A novel current splitting method is used to minimize the transistors gate–source voltages providing LV operation and ultra high current drive capability. High linearity and very high output impedance are achieved employing a novel resistor based current mirror avoiding conventional cascode structures to be used. The operation of the proposed COS has been verified through HSPICE simulations based on TSMC 0.18 μm CMOS technology parameters. Under supply voltage of ±0.7 V and bias current of 5 μA, it can deliver output currents as high as 14 mA with THD better than ?53 dB and extremely high output impedance of 320 MΩ while consuming only 29 μW. This makes the proposed COS to have ultra large current drive ratio (I_outmax/I_bias or the ratio of peak output current to the bias current of output branch transistors) of 2800. By increasing supply voltage to ±0.9 V, it can deliver extremely large output current of ±24 mA corresponding to 3200 current drive ratio while consuming only 42.9 μW and exhibiting high output impedance of 350 MΩ. Interestingly, the proposed COS is the first yet reported one with such extremely high output current and a THD even less than ?45 dB. Such ultra high current drive capability, high linearity and high output impedance make the proposed COS an outstanding choice for LV, VLP and high drive current mode circuits. The superiority of the proposed COS gets more significance by showing in this work that conventional COS can deliver only ±3.29 mA in equal condition. The proposed COS also exhibits high positive and negative power supply rejection ratio (PSRR+/PSRR?) of 125 dB and 130 dB, respectively. That makes it very suitable for LV, VLP mixed mode applications. The Monte Carlo simulation results are provided, which prove the outstanding robust performance of the proposed block versus process tolerances. Favorably the proposed COS resolves the major limitation of current output stages that so far has prevented designing high drive current mode circuits under low supply voltages. In brief, the deliberate combination of so many effective novel methods presents a wonderful phenomenal COS block to the world of science and engineering.     

Low voltage second-order alpha function synapse

This paper introduces a Transimpedance Amplifier (TIA) design capable of producing an incremental input resistance in the ohmic range, for input signals in the microampere range, such as are encountered in the design of instrumentation for electrochemical ampero-metric sensors, optical-sensing and current-mode circuits. This low input-resistance is achieved using an input stage incorporating negative feedback. In a Cadence simulation of an exemplary design using a 180 nm CMOS process and operating with?±?1.8 V supply rails, the input resistance is 1.05 ohms and the power dissipation is 93.6 µW. The bandwidth, for a gain of 100 dBohm, exceeded 9 MHz. For a 1µA, 1 MHz sinusoidal input signal the Total Harmonic Distortion, with this gain, is less than 1%. The input referred noise current with zero photodiode capacitance is 2.09 pA/√Hz and with a photodiode capacitance of 2pF is 8.52 pA/√Hz. Graphical data is presented to show the effect of a photodiode capacitance varying from 0.5 to 2 pF, when the TIA is used in optical sensing. In summary, the required very low input resistance, at a low input current level (µA) is achieved and furthermore a Table is included comparing the characteristics and a widely used Figure of Merit (FOM) for the proposed TIA and similar published low-power TIAs. It is apparent from the Table that the FOM of the proposed TIA is better than the FOMs of the other TIAs mentioned.

     

High Gain Modified Dual-Band and Dual-Circularly Polarized Array Antenna

Wireless Personal Communications - A novel design of double-layer dual-band circularly polarized array antennas (DDCPAAs) is presented in this paper. First, a DDCP single antenna is introduced as...     

Using anisotropic diffusion equations in pixon domain for image de-noising

Image enhancement is an essential phase in many image processing algorithms. In any image de-noising algorithm, it is a major concern to keep the interesting structures of the image. Such interesting structures in an image often correspond to the discontinuities in the image (edges). In this paper, we propose a new algorithm for image de-noising using anisotropic diffusion equations in pixon domain. In this approach, diffusion equations are applied on the pixonal model of the image. The algorithm has been examined on a variety of standard images and the performance has been compared with algorithms known from the literature. The experimental results show that in comparison with the other existing methods, the proposed algorithm has a better performance in de-noising and preserving image edges.     

Performance analysis of multi-antenna relay networks with imperfect channel estimation

In this paper, we present the performance of multi-antenna selective combining decode-and-forward (SC-DF) relay networks over independent but non-identical Nakagami-m fading channels with imperfect channel estimation. The outage probability, moment generating function (MGF) and symbol error probability (SEP) will be derived in closed-form using the SNR statistical characteristics. To make the analysis trackable, we have derived the MGF and SEP for integer values of fading severity, m. Also, to make the relations more simple, we develop high signal to noise ratio (SNR) analysis for the performance metrics of our system. Subsequently, we propose optimal and adaptive power allocation algorithms along with the equal power allocation method. Finally, for comparison with analytical formulas, we perform some Monte-Carlo simulations.     

Evaluation of performance enhancing proxies in internet over satellite

Performance enhancing proxies (PEPs) are widely used to improve the performance of TCP over high delay‐bandwidth product links and links with high error probability. In this paper we analyse the performance of using TCP connection splitting in combination with web caching via traces obtained from a commercial satellite system. We examine the resulting performance gain under different scenarios, including the effect of caching, congestion, random loss and file sizes. We show, via analysing our measurements, that the performance gain from using splitting is highly sensitive to random losses and the number of simultaneous connections, and that such sensitivity is alleviated by caching. On the other hand, the use of a splitting proxy enhances the value of web caching in that cache hits result in much more significant performance improvement over cache misses when TCP splitting is used. We also compare the performance of using different versions of HTTP in such a system. Copyright © 2003 John Wiley & Sons, Ltd.     

MIMO satellite communication with accelerated dual paths asynchronous design

This paper presents a novel asynchronous design approach for multiple input multiple output (MIMO) satellite communication (SatCom) systems. One of the main challenges for MIMO SatCom systems is that these are prone to transient faults that typically are attributable to radiation hazards. Hence, instead of using conventional synchronous circuits, we conceive our design using asynchronous circuits since it inherently has a high tolerance to transient fault. Additionally, we adopt accelerated dual paths (ADP) design into our system. By carefully arranging the data flow between the two paths, the ADP design approach can help to further accelerate the asynchronous system and increase the reliability of the system by circumventing transient faults induced delay, as well as tolerating latch-ups and other permanent faults. The numerical results show that this design approach provides promising results. For example, the proposed design can decrease the delay overhead of the entire system from 43.5 to 19.8 % at the fault rate of 400/clock cycle.     

Side-Channel Information Characterisation Based on Cascade-Forward Back-Propagation Neural Network

Traditional cryptanalysis assumes that an adversary only has access to input and output pairs, but has no knowledge about internal states of the device. However, the advent of side-channel analysis showed that a cryptographic device can leak critical information. In this circumstance, Machine learning is known as a powerful and promising method of analysing of side-channel information. In this paper, an experimental investigation on a FPGA implementation of elliptic curve cryptography (ECC) was conducted to explore the efficiency of side-channel information characterisation based on machine learning techniques. In this work, machine learning is used in terms of principal component analysis (PCA) for the preprocessing stage and a Cascade-Forward Back-Propagation Neural Network (CFBP) as a multi-class classifier. The experimental results show that CFBP can be a promising approach in characterisation of side-channel information.     

Modeling and optimization of the chamber of OWC system

Due to their non-polluting nature and environment friendliness, Renewable Energies have gained great deal of attention and deserve a substantial body of both theoretical and empirical research. Amongst other factors, the low operational cost and simple maintenance procedures attributed the Oscillating Water Column (OWC) are perhaps the main reasons why this system is the most used concept for the ocean wave energy capture.In this paper, through extensive experimental research various geometrical designs of an OWC system is investigated and the optimized set up for the maximum energy harness is obtained.The initial chamber dimensions were 10 × 50 × 53 cm with the chamber being placed in an open channel with wave-simulating equipment with dimensions of 16 × 0.7 × .05 m. For various chamber geometries, with the aid of a air rotameter and a Pitot tube equipped with a digital manometer, the outlet air flow and velocity from the chamber was measured and registered.The measurements were then interpreted to provide design data for the optimal geometry of the chamber that may yield the maximum conversion of wave energy to useful energy.