Should I e-collaborate with this group? A multilevel model of usage intentions

The use of online collaboration tools for virtual teamwork has been studied extensively, but mainly at the individual-level. We decided to examine the effect of macro-level factors (i.e., team attributes) and applied hierarchical linear modeling analysis to a sample of data collected from 96 individuals nested in 34 virtual teams. Our results suggested that the development of behavioral e-collaboration intentions by individual virtual team members was affected by their perceptions about the system, as described by individual-level IT use theories, and macro-level factors pertaining to the team. The collaboration technology was perceived to be less useful when employed to communicate with social loafers; and collective social loafing negatively influenced the teams’ potency assessments. After controlling for individual-level perceptions of system usefulness, team potency augmented team members’ intentions to use the online collaboration technology with similar teams. It also improved team performance.     

A longitudinal experimental study on the interaction effects of persuasion quality, user training, and first-hand use on user perceptions of new information technology

While prior research has investigated the main effects of external factors on user perceptions of a new IT, little work has been into the interaction effect of external factors on user perceptions. In a longitudinal experimental study, we examined the effect of the quality of persuasive argument, user training, and first-hand use on user perceptions of the new technology over time. We found that the effect of argument quality on users’ perceived ease of use was greater when users had no training. However, we did not find the same effect occurred due to perceived usefulness. We also found that first-hand use changed users’ perceived usefulness more over time when users received high quality arguments or when they had no training. While we found that first-hand use changed users’ perceived ease of use more when users received high quality arguments, first-hand use did not change users’ perceived ease of use differently whether they had or had not received prior training.     

Search advertising placement strategy: Exploring the efficacy of the conventional wisdom

Search advertising is one of the most important forms of electronic commerce. While click-through rates are considered a key measure of search advertising effectiveness by search providers, brand attention can also be a valuable objective. Our paper reports on an experiment that investigated how search advertisement placement affected search users’ brand recall and recognition. The results showed that semantically associated search ads generated significantly higher levels of brand attention than contextually associated ones. Significant interaction effects were found among search ad position, keyword association, and search result quality. Implications for decision makers are discussed.     

Data-intensive document clustering on graphics processing unit (GPU) clusters

Document clustering is a central method to mine massive amounts of data. Due to the explosion of raw documents generated on the Internet and the necessity to analyze them efficiently in various intelligent information systems, clustering techniques have reached their limitations on single processors. Instead of single processors, general-purpose multi-core chips are increasingly deployed in response to diminishing returns in single-processor speedup due to the frequency wall, but multi-core benefits only provide linear speedups while the number of documents in the Internet is growing exponentially. Accelerating hardware devices represent a novel promise for improving the performance for data-intensive problems such as document clustering. They offer more radical designs with a higher level of parallelism but adaptation to novel programming environments.In this paper, we assess the benefits of exploiting the computational power of graphics processing units (GPUs) to study two fundamental problems in document mining, namely to calculate the term frequency-inverse document frequency (TF-IDF) and cluster a large set of documents. We transform traditional algorithms into accelerated parallel counterparts that can be efficiently executed on many-core GPU architectures. We assess our implementations on various platforms, ranging from stand-alone GPU desktops to Beowulf-like clusters equipped with contemporary GPU cards. We observe at least one order of magnitude speedups over CPU-only desktops and clusters. This demonstrates the potential of exploiting GPU clusters to efficiently solve massive document mining problems. Such speedups combined with the scalability potential and accelerator-based parallelization are unique in the domain of document-based data mining, to the best of our knowledge.     

A leakage-aware L2 cache management technique for producer-consumer sharing in low-power chip multiprocessors

This paper proposes a novel leakage management technique for applications with producer-consumer sharing patterns. Although previous research has proposed leakage management techniques by turning off inactive cache blocks, these techniques can be further improved by exploiting the various run-time characteristics of target applications in CMPs. By exploiting particular access sequences observed in producer-consumer sharing patterns and the spatial locality of shared buffers, our technique enables a more aggressive turn-off of L2 cache blocks of these buffers. Experimental results using a CMP simulator show that our proposed technique reduces the energy consumption of on-chip L2 caches, a shared bus, and off-chip memory by up to 31.3% over the existing cache leakage power management techniques with no significant performance loss.     

Admission control mechanism and performance analysis based on stochastic automata networks formalism

IEEE 802.16 has been designed to support QoS (Quality of Service) in Wireless broadband Metropolitan Networks (WMAN), and specifically in the access networks. To achieve this, the IEEE 802.16.e amendment introduces the service differentiation by five service classes (UGS, ertPS, rtPS, nrtPS and BE). To maintain the QoS of active connections and to avoid any congestion in the network, an Admission Control (AC) is defined. AC aims to accept or reject a new connection according to the negotiated parameters and the availability of resources in the network. This mechanism is not standardized and let to the operators. We tackle this point, by proposing in this study a new Admission Control (AC) that improves the QoS of BE traffic by avoiding a strict bandwidth assignment of other traffics (rtPS and nrtPS) as is defined in major previous studies. The proposed mechanism is based on token bucket for rtPS, nrtPS and BE traffics in order to reduce lightly the number of accepted connections and to improve considerably the number of accepted BE connections. To evaluate the performance of the proposed scheme, we use PEPS (Performance Evaluation of Parallel Systems) which is a powerful tool based on models which can be described with Stochastic Automata Networks (SAN). PEPS can solve complex models with a large state space and with many synchronized events. Therefore, we show that this tool is suitable for wireless network, and specifically for the proposed scheme, toward numerical results we show as we expected that our proposed AC outperform the classical one by reducing lightly the performance of other service classes.     

C-AMTE: A location mechanism for flexible cache management in chip multiprocessors

This paper describes Constrained Associative-Mapping-of-Tracking-Entries (C-AMTE), a scalable mechanism to facilitate flexible and efficient distributed cache management in large-scale chip multiprocessors (CMPs). C-AMTE enables fast locating of cache blocks in CMP cache schemes that employ one-to-one or one-to-many associative mappings. C-AMTE stores in per-core data structures tracking entries to avoid on-chip interconnect traffic outburst or long distance directory lookups. Simulation results using a full system simulator demonstrate that C-AMTE achieves improvement in cache access latency by up to 34.4%, close to that of a perfect location strategy.     

A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms

Networks-on-Chip (NoCs) can be used for test data transportation during manufacturing tests. On one hand, NoC can avoid dedicated Test Access Mechanisms (TAMs), reducing long global wires, and potentially simplifying the layout. On the other hand, (a) it is not known how much wiring is saved by reusing NoCs as TAMs, (b) the impact of reuse-based approaches on test time is not clear, and (c) a computer aided test tool must be able to support different types of NoC designs. This paper presents a test environment where the designer can quickly evaluate wiring and test time for different test architectures. Moreover, this paper presents a new test scheduling algorithm for NoC TAMs which does not require any NoC timing detail and it can easily model NoCs of different topologies. The experimental results evaluate the proposed algorithm for NoC TAMs with an exiting algorithm for dedicated TAMs. The results demonstrate that, on average, 24% (up to 58%) of the total global wires can be eliminated if dedicated TAMs are not used. Considering the reduced amount of dedicated test resources with NoC TAM, the test time of NoC TAM is only, on average, 3.88% longer compared to dedicated TAMs.     

CAFES: A framework for intrachip application modeling and communication architecture design

This paper describes CAFES, an extensible, open-source framework supporting several tasks related to high-level modeling and design of applications employing complex intrachip communication infrastructures. CAFES comprises several built-in models, including application, communication architecture, energy consumption and timing models. It also includes a set of generic and specific algorithms and additional supporting tools, which jointly with the cited models allow the designer to describe and evaluate applications requirements and constraints on specified communication architectures. Several examples of the use of CAFES underline the usefulness of the framework. Some of these are approached in this paper: (i) a realistic application captured at high-level that has its computation time estimated after mapping at the clock cycle level; (ii) a multi-application system that is automatically mapped to a large intrachip network with related tasks occupying contiguous areas in the chip layout; (iii) a set of mapping algorithms explored to define trade-offs between run time and energy savings for small to large intrachip communication architectures.     

Static timing analysis for modeling QoS in networks-on-chip

Networks-on-chip (NoCs) are used in a growing number of SoCs and multi-core processors. Because messages compete for the NoC’s shared resources, quality of service and resource allocation are major concerns for system designers. In particular, a model for the properties of packet delivery through the network is desirable. We present a methodology for packet-level static timing analysis in NoCs. Our methodology quickly and accurately gauges the performance parameters of a virtual-channel wormhole NoC without simulation. The network model can handle any topology, link capacities, and buffer sizes. It provides per-flow delay analysis that is orders-of-magnitude faster than simulation while being significantly more accurate than prior static modeling techniques. Using a carefully derived and reduced Markov chain, the model can statically represent the dynamic network state. Usage of the model in a placement optimization problem is shown as an example application.