Performance Analysis of Arbitration Policies for SoC Communication Architectures

As technology scales toward deep submicron, the integration of a large number of IP blocks on the same silicon die is becoming technically feasible, thus enabling large-scale parallel computations, such as those required for multimedia workloads. The communication architecture is becoming the bottleneck for these multiprocessor Systems-on-Chip (SoC), and efficient contention resolution schemes for managing simultaneous access requests to the shared communication resources are required to prevent system performance degradation. The contribution of this work is to analyze the impact on multiprocessor SoC performance of different bus arbitration policies under different communication patterns, showing the distinctive features of each policy and the strong correlation of their effectiveness with the communication requirements of the applications. Beyond traditional arbitration schemes such as round robin and TDMA, another policy is considered that periodically allocates a temporal slot for contention-free bus utilization to a processor which needs fixed predictable bandwidth for the correct execution of its time-critical task. The results are derived on a complete and scalable multiprocessor SoC simulation platform based on SystemC, whose software support includes a complete embedded multiprocessor OS (RTEMS). The communication architecture is AMBA compliant, and we exploit the flexibility of this multi-master commercial standard, which does not specify the arbitration algorithm, to implement the explored contention resolution schemes.     

A pre-placement individual net length estimation model and an application for modern circuits

With the advances in integrated circuit (IC) technology, managing the individual and total interconnect is becoming one of the main challenges facing designers. An individual a-priori length estimation model can be a useful tool in helping designers obtain lower net lengths and congestion of interconnect. In this paper, the main characteristics that need to be considered while designing an individual a-priori length estimation technique for today's integrated circuits are discussed. A model that includes some of the most prevalent characteristics is designed and tested using the most current benchmark circuits released by IBM. In addition, one application of the length estimation is proposed in which a predictor-corrector framework for clustering that can be used to improve the results of placement is implemented. This model shows that the corrector step can improve the final placement results by up to 33% for special cases.     

Joint near-lossless compression and watermarking of still images for authentication and tamper localization

A system is presented to jointly achieve image watermarking and compression. The watermark is a fragile one being intended for authentication purposes. The watermarked and compressed images are fully compliant with the JPEG-LS standard, the only price to pay being a slight reduction of compression efficiency and an additional distortion that can be anyway tuned to grant a maximum preset error. Watermark detection is possible both in the compressed and in the pixel domain, thus increasing the flexibility and usability of the system. The system is expressly designed to be used in remote sensing and telemedicine applications, hence we designed it in such a way that the maximum compression and watermarking error can be strictly controlled (near-lossless compression and watermarking). Experimental results show the ability of the system to detect tampering and to limit the peak error between the original and the processed images.     

Optimal gate sizing using a self-tuning multi-objective framework

In this paper, we present a self-tuning multi-objective framework for geometric programming that provides a fine trade-off between the competing objectives. The significance of this framework is that the designer does not need to perform any tuning of weights of objectives. The proposed framework is applied to gate sizing and clock network buffer sizing problems. In gate sizing application, power consumption is reduced on average by 86% while delay sees only an increase of 34 ns. In clock network butter sizing application, our framework results in a significant reduction in power, 57%, and an improvement of 31 ps in skew.     

Design of 3.1–10.6 GHz ultra-wideband CMOS low noise amplifier with current reuse technique

A new low complexity ultra-wideband 3.1–10.6 GHz low noise amplifier (LNA), designed in a chartered 0.18 μm RFCMOS technology, is presented in this paper. The ultra-wideband LNA only consists of two simple amplifiers with an inter-stage inductor connected. The first stage utilizing a resistive current reuse and dual inductive degeneration techniques is used to attain a wideband input matching and low noise figure. A common source amplifier with inductive peaking technique as the second stage achieves high flat gain and wide the −3 dB bandwidth of the overall amplifier simultaneously. The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB, a high reverse isolation of −45 dB and a good input/output return losses are better than −10 dB in the frequency range of 3.1–10.6 GHz. An excellent noise figure (NF) of 2.8–4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V. An input-referred third-order intercept point (IIP3) is −7.1 dBm at 6 GHz. The chip area including testing pads is only 0.8 mm × 0.9 mm.     

Capacitance DNA bio-chips improved by new probe immobilization strategies

Label-free DNA detection plays a crucial role in developing point-of-care biochips. Capacitance detection is a promising technology for label-free detection. However, data published in literature often show evident time drift, large standard deviation, scattered data points, and poor reproducibility. To address these problems, mercapto-hexanol or similar alkanethiols are usually considered as blocking agents. The aim of the present paper is to investigate new blocking agents to further improve DNA probe surfaces. Data from AFM, SPR, florescence microscopy, and capacitance measurements are used to investigate new lipoate and ethylene-glycol molecules. The new surfaces offer further improvements in terms of diminished detection errors. Film structures are investigated at the nano-scale to justify the detection improvements in terms of probe surface quality. This study demonstrates the superiority of lipoate and ethylene-glycol molecules as blocking candidates when immobilizing molecular probes onto spot surfaces in label-free DNA biochip.     

Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM

As technology continues to scale, maintaining important figures of merit of Static Random Access Memories (SRAMs), such as power dissipation and an acceptable Static Noise Margin (SNM), becomes increasingly challenging. In this paper, we address SRAM instability and power (leakage) dissipation in scaled-down technologies by presenting a novel design flow for simultaneous power minimization, performance maximization and process variation tolerance (P3) optimization of nano-CMOS circuits. The 45 and 32 nm technology node standard 6-Transistor (6T) and 8T SRAM cells are used as example circuits for demonstration of the effectiveness of the flow. Thereafter, the SRAM cell is subjected to a dual threshold voltage (dual-V_Th) assignment based on a novel statistical Design of Experiments-Integer Linear Programming (DOE-ILP) approach. Experimental results show 61% leakage power reduction and 13% increase in the read SNM. In addition, process variation analysis of the optimized cell is conducted considering the variability effect in twelve device parameters. To the best of the authors' knowledge, this is the first study which makes use of statistical DOE-ILP for optimization of conflicting targets of stability and power in the presence of process variations in SRAMs.     

Numerical and experimental characterization of antenna positioning in a dual-radio mesh router

This paper investigates the influence of the position of the antennas in a dual-radio mesh router by characterizing the router components from an electromagnetic point of view. Since the behavior of a wireless router equipped with multiple devices and antennas can be affected by mutual coupling among several close conducting bodies, numerical and experimental tests are carried out to provide some suggestions for an accurate positioning of the antennas. A reference configuration is implemented in an electromagnetic Computer-Aided Design (CAD) simulator. The most significant numerical results are validated by performing a campaign of measurements in anechoic chamber and deploying a testbed for the derivation of the experimental values of throughput, return loss, power density, and directivity.     

Reproducing consistent wireless protocol performance across environments

Full scale experimentation with wireless networks in deployment environments is difficult. Therefore a common validation technique is to test a prototype network in a convenient environment prior to deployment. In this paper, we consider the problem of obtaining comparable protocol performance when the test and deployment environments differ in RF propagation environment and/or inter-node spacing. To achieve comparable protocol behavior in the two settings, we propose the concept of “link usage spectrum”. Based on the hypothesis that the link usage spectrum is a gross predictor for network performance, we show how to replicate in the test setting the link usage spectrum of the protocol that is expected in the deployment setting. We show our technique for achieving comparable protocol behavior via experiments and simulations in multiple indoor and outdoor propagation environments. The link usage spectrum is protocol specific; we illustrate for a family of protocols how the link usage spectrum is calculated analytically, from the protocol metric for choosing forwarding links in the network, and how power scaling can be used to match the link usage spectrum across networks.